2.1 Verilog UDP Basics

Category Advanced Verilog Tutorial

The built-in gate primitives introduced in gate-level modeling, such as and, or, nor, etc., are all part of the standard primitives provided by Verilog, commonly referred to as built-in primitives.

Additionally, Verilog allows users to write their own primitives, known as User Defined Primitives (UDP).

In UDP, no other modules or primitives can be called, and the calling method is identical to that of gate-level primitives.

There are mainly two types of UDPs, which will be introduced one by one later.

Combinational Logic UDP: The output is solely determined by the combination of input signals.
Sequential Logic UDP: The next output value depends not only on the current input values but also on the current internal state.

UDP Definition

The definition of UDP does not rely on module definitions, so it can appear outside of module definitions or be defined separately in a file.

The format for defining UDP is as follows:

Example

primitive UDP_name (
  output_name,
  list_of_input);

  output_declaration;
  list_of_input_declaration;
  [reg_declaration];
  [initial_statement];

  table
    list_of_table_entries;
  endtable
endprimitive

UDP Explanation

Port Declaration:

1. The port declaration part is similar to that of a module. You can list the port signals in the port list and then specify their types within the primitive entity, or directly specify their types in the port list.
1. Input ports can only be scalars (i.e., 1 bit), and multiple input ports are allowed.
1. There is only one output port allowed, which must be a scalar (i.e., 1 bit), and the output port must appear in the first position of the port list. Multiple output ports are absolutely not allowed.
1. The output port is declared with the output keyword, and for sequential logic UDPs that need to save state, the output port must also be declared as reg type.
1. UDP does not support inout port types.

Initialization

The initial statement can be used to initialize the output port (reg type) of a sequential logic UDP, which is optional.

State Table

1. The UDP state table is the most important part of the UDP, declared with the table keyword. It defines how the output value is obtained based on the input state and the current state, similar to a logic truth table.
1. The entries in the state table can be 0, 1, or x. UDP cannot handle z values, so z values passed to the UDP are treated as x.

-0.1 Digital Logic Design

-0.2 Verilog Coding Style

-0.3 Verilog Code Guide

-1.1 Verilog Gate Types

-1.2 Verilog Switch-Level Modeling

-1.3 Verilog Gate Delay