5.2 Verilog Module Instantiation
Category Verilog Tutorial
Keywords: Instantiation, generate, full adder, hierarchical access
Referring to another module within a module and connecting its ports is called module instantiation. Module instantiation establishes a level of description. Signal ports can be associated by position or name, and port connections must also follow certain rules.
Named Port Connection
This method connects the ports of the module to be instantiated with external signals according to their names. The order of the ports is arbitrary and can be different from the order of the declared ports of the referenced module, as long as the port names match the external signals.
Here is an example of instantiating a 1-bit full adder:
Example
full_adder1 u_adder0(
.Ai(a[0]),
.Bi(b[0]),
.Ci(c == 1'b1 ? 1'b0 : 1'b1),
.So(so_bit0),
.Co(co_temp[0]));
If some output ports do not need to be connected externally, they can be left unconnected or even removed during instantiation. Generally, input ports cannot be deleted during instantiation, otherwise, the compiler will report an error, while output ports can be deleted. For example:
Example
//output port Co unconnected
full_adder1 u_adder0(
.Ai(a[0]),
.Bi(b[0]),
.Ci(c == 1'b1 ? 1'b0 : 1'b1),
.So(so_bit0),
.Co());
//output port Co removed
full_adder1 u_adder0(
.Ai(a[0]),
.Bi(b[0]),
.Ci(c == 1'b1 ? 1'b0 : 1'b1),
.So(so_bit0));
Ordered Port Connection
This method matches the ports of the module to be instantiated with external signals according to the order of the ports when the module is declared, and the position must be strictly consistent. For example, the code for instantiating a 1-bit full adder can be changed to:
full_adder1 u_adder1(
a[1], b[1], co_temp[0], so_bit1, co_temp[1]);
Although the code may occupy relatively less space in writing, the readability of the code is reduced, and it is not easy to debug. Sometimes in large designs, there may be many ports, and the order of port signals may change from time to time. At this time, using ordered port connection for module instantiation is obviously inconvenient. Therefore, it is recommended to use the named port method for module instantiation.
Port Connection Rules
Input Ports
During module instantiation, from the outside of the module, input ports can be connected to wire or reg type variables. This is different from the module declaration, from the inside of the module, input ports must be wire type variables.
Output Ports
During module instantiation, from the outside of the module, output ports must be connected to wire type variables. This is different from the module declaration, from the inside of the module, output ports can be wire or reg type variables.
Inout Ports
During module instantiation, from the outside of the module, inout ports must be connected to wire type variables. This is the same as the module declaration.
Dangling Ports
During module instantiation, if some signals do not need to be connected and interacted with external signals, they can be left dangling, that is, the port is left blank during instantiation, as mentioned in the above examples.
When the output port is normally dangling, it can even be deleted during instantiation.
When the input port is normally dangling, the logical function of the dangling signal is high-impedance state (logical value is z). However, dangling input ports generally cannot be deleted during instantiation, otherwise, the compiler will report an error, for example:
Example
//The following code will report a Warning during compilation
full_adder4 u_adder4(
.a(a),
.b(b),
.c(),
.so(so),
.co(co));
Example
//If the module full_adder4 has an input port c, the following code will report an Error during compilation
full_adder4 u_adder4(
.a(a),
.b(b),
.so(so),
.co(co));
Generally, it is recommended not to leave input ports dangling. When there are no other external connections, assign a constant value to it, for example:
Example
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5.2 Verilog Module Instantiation