4.5 Verilog Conditional Statements
Category Verilog Tutorial
Keywords: if, selector
Conditional Statements
Conditional (if) statements are used to control the execution of statements based on condition checks.
Conditional statements are declared using the keywords if and else, with the condition expression enclosed in parentheses.
The structure of conditional statements is as follows:
if (condition1) true_statement1 ;
else if (condition2) true_statement2 ;
else if (condition3) true_statement3 ;
else default_statement ;
When executing an if statement, if condition1 is true, true_statement1 is executed; if condition1 is false and condition2 is true, true_statement2 is executed; and so on.
The else if and else structures can be omitted, meaning a single if condition and a set of execution statements true_statement1 can constitute an execution process.
Multiple else if structures can be stacked, not limited to 1 or 2.
The execution statements like true_statement1 can be a single statement or multiple statements. If there are multiple execution statements, they need to be enclosed with the begin and end keywords.
The following code implements the functionality of a 4-way selector.
Example
module mux4to1(
input [1:0] sel ,
input [1:0] p0 ,
input [1:0] p1 ,
input [1:0] p2 ,
input [1:0] p3 ,
output [1:0] sout);
reg [1:0] sout_t ;
always @(*) begin
if (sel == 2'b00)
sout_t = p0 ;
else if (sel == 2'b01)
sout_t = p1 ;
else if (sel == 2'b10)
sout_t = p2 ;
else
sout_t = p3 ;
end
assign sout = sout_t ;
endmodule
The testbench code is as follows:
Example
`timescale 1ns/1ns
module test ;
reg [1:0] sel ;
wire [1:0] sout ;
initial begin
sel = 0 ;
#10 sel = 3 ;
#10 sel = 1 ;
#10 sel = 0 ;
#10 sel = 2 ;
end
mux4to1 u_mux4to1 (
.sel (sel),
.p0 (2'b00), //path0 is assigned to 0
.p1 (2'b01), //path1 is assigned to 1
.p2 (2'b10), //path2 is assigned to 2
.p3 (2'b11), //path3 is assigned to 3
.sout (sout));
//finish the simulation
always begin
#100;
if ($time >= 1000) $finish ;
end
endmodule
The simulation results are as follows.
As shown in the figure, the output signal matches the selection signal and the input signal states.
In the example, the if condition executes only one statement each time, without using the begin and end keywords. However, in an if-if-else format, even if there is only one execution statement, not using the begin and end keywords can cause ambiguity.
For example, in the following code, although the format is differentiated, it is ambiguous which if condition the else corresponds to.
Example
if(en)
if(sel == 2'b1)
sout = p1s ;
else
sout = p0 ;
Typically, compilers follow the nearest principle, making the else correspond to the nearest if (the second if in the example).
However, this writing style is clearly non-standard and unsafe.
Therefore, including the begin and end keywords in conditional statements is a good habit.
For example, the above code can be slightly modified to avoid ambiguity in writing.
Example
if(en) begin
if(sel == 2'b1) begin
sout = p1s ;
end
else begin
sout = p0 ;
end
end
Source Code Download
-1.3 Verilog Environment Setup
-2.2 Verilog Numerical Representation
-2.5 Verilog Compile Instructions
-3.1 Verilog Continuous Assignment
-4.1 Verilog Process Structure
-4.2 Verilog Process Assignment
- 4.5 Verilog Conditional Statements
-4.6 Verilog Multi-way Branch Statements
-4.8 Verilog Process Continuous Assignment
-5.1 Verilog Modules and Ports
-5.2 Verilog Module Instantiation
-5.3 Verilog Parameterized Instantiation
-6.4 Verilog Competition and Hazards
-6.6 Verilog Simulation Stimulus
-7.2 Verilog Parallel FIR Filter Design
-7.3 Verilog Serial FIR Filter Design
-7.4 Verilog CIC Filter Design
-8.1 Verilog Numerical Conversion
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