1.1 Verilog Tutorial

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1.1 Verilog Tutorial

Category Verilog Tutorial

Verilog HDL (short for Verilog) is a hardware description language used for the system design of digital circuits. It can model various levels of abstraction in design, such as algorithmic, gate, and switch levels.

Verilog has inherited a variety of operators and structures from the C language. Compared to another hardware description language, VHDL, its syntax is not very strict, the code is more concise, and it is easier to learn.

Verilog not only defines the syntax but also defines clear simulation semantics for the syntax structure. Therefore, digital models written in Verilog can be verified using Verilog simulators.

Who is this tutorial suitable for

This tutorial is mainly designed for beginners in Verilog.

Students with some foundation in Verilog can also learn and communicate in the advanced and example sections.

Knowledge you need to know before reading this tutorial

Before studying this tutorial, you need to understand some basic information about digital circuits.

If you have some understanding of the C language, it will help you to quickly get started with Verilog.

First Verilog Design

4-bit wide decimal counter:

Example

module counter10(
    // Port definition
    input rstn,  // Reset end, low effective
    input clk,   // Input clock
    output [3:0] cnt,  // Count output
    output cout);  // Overflow bit

    reg [3:0] cnt_temp;  // Counter register
    always @(posedge clk or negedge rstn) begin
        if (!rstn) begin  // Reset, count to 0
            cnt_temp <= 4'b0;
        end
        else if (cnt_temp == 4'd9) begin  // Count to 10 cycles, count to 0
            cnt_temp <= 4'b000;
        end
        else begin  // Count plus 1
            cnt_temp <= cnt_temp + 1'b1;
        end
    end

    assign cout = (cnt_temp == 4'd9);  // Output cycle bit
    assign cnt = cnt_temp;  // Output real-time timer

endmodule

Cat Me

I have been engaged in FPGA design and IC design. I used to design more with VHDL language during my student days, and I have been using Verilog ever since. To facilitate my own syntax query and to provide a convenient learning path for other scholars, I have written this tutorial. It should be noted:

(1) The content of the tutorial is written from my own learning perspective, which may be easier to learn. If there are any inappropriate places, please point out and let's make progress together.
(2) When a digital module is designed with Verilog and simulated, it is necessary to add stimulation externally, and the stimulation file is called testbench. Sometimes the design of the testbench may be more complex than the digital module itself. Therefore, when introducing the basic syntax of Verilog before, there was almost no simulation. When introducing behavioral and timing knowledge later, more simulations will be used for explanation.

Contact: Think · In · Hardware

The entire tutorial is manually collected, organized, and written by me, and all designs and simulations are original or improved. If you benefit from it, your appreciation or attention will be the most unscrupulous support, encouraging my hungry soul to write a full chapter.

1.1 Verilog Tutorial
1.2 Introduction to Verilog
1.3 Setting up the Verilog Environment
1.4 Verilog Design Methods
2.1 Basic Syntax of Verilog
2.2 Numerical Representation in Verilog
2.3 Data Types in Verilog
2.4 Expressions in Verilog
2.5 Verilog Compile Instructions
3.1 Continuous Assignment in Verilog
3.2 Time Delay in Verilog
4.1 Process Structure in Verilog
4.2 Process Assignment in Verilog
4.3 Timing Control in Verilog
[4.4 Statement Blocks in Verilog](verilog-statements-block

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