0.1 Digital Logic Design
Classification Advanced Verilog Tutorial
Preface
This tutorial primarily covers knowledge involved in digital IC design (Digital Integrated Circuit Design) using Verilog, with a stronger emphasis on the safe, stable, and convenient implementation of digital circuits. It is quite appropriate to consider this tutorial as an advanced version of the "Verilog Tutorial".
The content mainly includes: low-level (Chapter 1 Gate-Level Modeling, Chapter 2 User-Defined Primitives UDP, Chapter 9 Logic Synthesis), timing (Chapter 3 Timing Analysis), optimization (Chapter 4 Synchronization and Asynchrony, Chapter 5 Reset and Clock, Chapter 6 Low Power Design), and techniques (Chapter 7 System Tasks, Chapter 8 Programming Language Interface PLI).
Who is this tutorial suitable for
This tutorial is mainly designed for students with a certain foundation in Verilog and digital circuits.
Before reading this tutorial, please refer to the basic version "Verilog Tutorial".
Cat Me
The basic version "Verilog Tutorial" has received many corrections and inquiries from students, and I have made modifications and replies in my spare time. I am very grateful for the verbal encouragement and support from scholars, and due to the limitations of the reply mechanism, I cannot provide timely feedback for the emotions and gratitude in my heart. I also hope that this advanced tutorial can bring more benefits to you who are hardworking and kind.
Contact Person: Think · In · Hardware
The entire tutorial is manually collected, organized, and written by me, all design simulations are original or improved, and all source codes are also attached at the end. If you benefit from it, your appreciation or attention will be the most direct and effective support, warming me to condense more fruits of digital design.
Sentimental Admonition
I am the least fond of those greasy bowls of soul chicken soup, but I find the bone soup brewed by the masses of poets "Muzhe" quite fragrant. Here is a quote for everyone, and also for myself, to encourage.
At this age, I am still chasing the night bus of this city in a mess, but I am also entangled in comparing the price differences of different takeout merchants. I like weekends but also fear weekends, laughter and joy are the entertainment and relaxation I briefly experience on TV, and after the joy is over, I can feel the cold and loneliness of this city even more. Full wings are blind self-confidence in the ivory tower, and the world is not familiar with the cruel reality of life. I have been away from home for more than ten years, and I have been studying and working in the so-called big cities, not afraid of the physical toil and labor, but afraid of the spiritual reliance. Whip the horse, return to the hometown in splendid attire is the pursuit of every man's life, and the pride and self-respect are the arrogance in the bones of every man. But as the years permeate, they are ultimately worn down by reality and the secular world has extinguished dreams.
An encouraging smile, a nod of affirmation, a helping hand, a confiding conversation, will let me see the self before being smoked by the fireworks, see those grievances that will not make people feel distressed. Living in the world, suddenly realized, there should be a great ordinary, do not think the world is floating because of the small, do not think there is no light in the future because of the vague.
From this moment on, try to make up for regrets, try to grasp the hearts of wisdom gushing like a spring, and feel the excitement and emotion from the depths of the soul. When you are a little better than others, others will be jealous, when you are much better than others, others will only envy, and when you are in a worse foundation and worse conditions than others, and you can't let others surpass, others can only worship. An old saying, believe in yourself. Because life, you are life! Because miracles, you are a miracle!
- 0.1 Digital Logic Design
-0.3 Verilog Code Specification
-1.2 Verilog Switch-Level Modeling
-2.1 Basic Knowledge of Verilog UDP
-[2.2 Verilog Combinational Logic UDP](verilog2-udp