8.4 Verilog ACC Subprograms
Category Advanced Verilog Tutorial
Functional Features
The main functionalities of ACC subprograms include:
Reading specific object-related information from internal data structures
Writing specific object-related information into internal data structures
The object types that ACC subprograms can operate on include:
Module instances, module ports, end-to-end paths of modules, and paths between modules
Top-level modules
Primitive instances and primitive ports
Variable types such as wire, reg, parameter, integer, time, real, etc.
Timing checks
Named events
The main features of ACC subprograms are:
All start with the prefix acc_
Must call acc_initialize() at the beginning for environment initialization
Must call acc_close() when exiting
When using functions in the ACC library, the header file acc_user.h must be included
The concept of handles is used to access objects. A handle is a predefined data type pointing to a specific object in the design. Once a handle is obtained, all information about the object can be accessed. This is similar to the concept of file handles in C language. Handles are declared with the keyword handle.
The main types of ACC subprograms include:
Handle subprograms (handle): Return handles to objects in the design, always prefixed with acc_handle_
Next subprograms (next): Return handles to the next object in a specific object set in the design, always prefixed with acc_next_, and take the referenced object as a parameter.
Value Change Link subprograms (VCL): Add and remove objects from a list of objects monitoring value changes, always prefixed with acc_vcl_, and have no return value.
Fetch subprograms: Can extract hierarchical path and other attribute information, always prefixed with acc_fetch_.
Miscellaneous subprograms: Used for performing some miscellaneous operations related to access subprograms, such as acc_initialize() and acc_close() which are both miscellaneous subprograms.
Modify subprograms: Can modify internal data structures.
For a complete list of ACC subprograms and their simple usage instructions, refer to the next section "8.5 List of ACC Subprograms".
Example of ACC Subprograms
The following are examples of using some ACC subprograms, mainly illustrating the basic process of designing Verilog system tasks with ACC subprograms.
Design Requirements
This design involves a system task for monitoring a counter.
On one hand, the system task monitors the value of the counter in Verilog, and on the other hand, it also performs software counting when detecting the Verilog count clock, and compares the software and hardware count values to check the correctness of the hardware logic. At the same time, when the counter reaches a specific value, it outputs the values of some signal variables.
This design concept is also a common scenario for PLI interfaces. Software completes a logical function, called CModel. Then the hardware also completes the same logical function using Verilog. Through the PLI interface program, software and hardware programs can be executed simultaneously and the results can be compared to verify the correctness of the hardware logic design.
Design Analysis
The PLI interface part uses the Value Change Link subprogram to monitor the clock. Once the rising edge of the clock arrives, it calls the software function to perform software counting and compare the software and hardware count values.
Software Design
The software design code is as follows, with details explained in the comments, saved in the file monitor_gyc.c.
Example
```c
include "acc_user.h"
handle hand_rstn, hand_clk, hand_cnt, hand_cout; int cnt_soft = 0; // Value of the software counter int cout_soft = 0; // Overflow bit of the software counter
// Software counting and comparison function void act_monitor() { p_acc_value value; // Declare a structure variable defined in ACC // Read the value of the signal variable in Verilog, string type char *rstn_rtl_str = acc_fetch_value(hand_rstn, "%d", value); char *clk_rtl_str = acc_fetch_value(hand_clk, "%d", value); char *cnt_rtl_str = acc_fetch_value(hand_cnt, "%d", value); char *cout_rtl_str = acc_fetch_value(hand_cout, "%d", value);
// Convert string to integer
int rstn_rtl = atoi(rstn_rtl_str);
int clk_rtl = atoi(clk_rtl_str);
int cnt_rtl = atoi(cnt_rtl_str);
int cout_rtl = atoi(cout_rtl_str);
// Software counter
// Reset
if (!rstn_rtl) {
cnt_soft = 0;
cout_soft =
English: The simulation results log is as follows.
The log indicates that the hardware and software count comparison is correct, and the state of the counter completing a cycle count is also normal.
Download the source code for this chapter
8.4 Verilog ACC Subprograms