4.3 Verilog Timing Control
Classification Verilog Tutorial
Keywords: Timing Control, Event Triggering, Edge Triggering, Level Triggering
Verilog provides two major categories of timing control methods: delay control and event control. Event control is mainly divided into edge-triggered event control and level-sensitive event control.
Delay Control
Delay-based timing control appears in expressions, specifying the time interval between the start and completion of a statement's execution.
Delays can be numbers, identifiers, or expressions.
Depending on the position in the expression, delay control can be further divided into conventional delays and embedded delays.
Conventional Delay
When encountering a conventional delay, the statement must wait for a certain period before assigning the calculated result to the target signal.
The format is: #delay procedural_statement, for example:
reg value_test;
reg value_general;
#10 value_general = value_test;
Another way to write this delay method is to make the hash sign # a separate delay execution statement, for example:
#10;
value_single = value_test;
Embedded Delay
When encountering an embedded delay, the statement first saves the calculated result and then waits for a certain period before assigning it to the target signal.
Embedded delay control is added after the assignment operator. For example:
reg value_test;
reg value_embed;
value_embed = #10 value_test;
It should be noted that the effects of these two delay control methods are different.
When the right side of the delay statement's assignment operator is a constant, both delay controls can achieve the same delay assignment effect.
When the right side of the delay statement's assignment operator is a variable, the two delay controls may produce different delay assignment effects.
For example, the following simulation code:
Example
`timescale 1ns/1ns
module test;
reg value_test;
reg value_general, value_embed, value_single;
//signal source
initial begin
value_test = 0;
#25; value_test = 1;
#35; value_test = 0; //absolute 60ns
#40; value_test = 1; //absolute 100ns
#10; value_test = 0; //absolute 110ns
end
//(1)general delay control
initial begin
value_general = 1;
#10 value_general = value_test; //10ns, value_test=0
#45 value_general = value_test; //55ns, value_test=1
#30 value_general = value_test; //85ns, value_test=0
#20 value_general = value_test; //105ns, value_test=1
end
//(2)embedded delay control
initial begin
value_embed = 1;
value_embed = #10 value_test; //0ns, value_test=0
value_embed = #45 value_test; //10ns, value_test=0
value_embed = #30 value_test; //55ns, value_test=1
value_embed = #20 value_test; //85ns, value_test=0
end
//(3)single delay control
initial begin
value_single = 1;
#10;
value_single = value_test; //10ns, value_test=0
#45;
value_single = value_test; //55ns, value_test=1
#30;
value_single = value_test; //85ns, value_test=0
#20;
value_single = value_test; //105ns, value_test=1
end
always begin
#10;
if ($time >= 150) begin
$finish;
end
end
endmodule
The simulation results are as follows. As shown in the figure:
(1) The results of the two expressions of general delay are consistent.
(2) General delay assignment method: After encountering a delay statement, it first delays for a certain period, and then assigns the current operand to the target signal, without the characteristic of "inertial delay," and does not miss relatively narrow pulses.
(3) Embedded delay assignment method: After encountering a delay statement, it first calculates the result on the right side of the expression, and then delays for a certain period before assigning it to the target signal.
Next, let's analyze the assignment process of embedded delay:
value_embed = #10 value_test; //0ns, value_test=0
At 0ns, this delay statement is executed.
First, 0 is assigned to the signal value_embed, and after a delay
4.3 Verilog Timing Control