3.3 Verilog Setup Time and Hold Time

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3.3 Verilog Setup Time and Hold Time

Category Advanced Verilog Tutorial

Keywords: Setup Time, Hold Time

For digital systems, setup time and hold time are fundamental to digital circuit timing. The stability of a digital circuit system largely depends on whether the timing meets the setup and hold times. Therefore, this entire section is dedicated to a detailed explanation of the concepts of setup and hold times.

Basic Concepts

Setup time is the minimum amount of time before the clock event arrives that data must remain stable for it to be correctly sampled by the clock.

Hold time is the minimum amount of time after the clock event arrives that data must remain stable for it to be accurately transmitted by the circuit.

It can be understood simply as: before the clock arrives, data needs to be prepared in advance; after the clock arrives, data needs to remain stable for a period. Setup time and hold time together form the window of data stability, as shown in the figure below.

《1.3 Gate Delay》 has already introduced a simple D flip-flop. Below, let's look at a typical rising-edge D flip-flop to explain the origin of setup and hold times.

G1~G4 NAND gates form a维持阻塞 circuit, and G5~G6 form an RS flip-flop.

The clock directly acts on G2/G3 gates; when the clock is low, G2/G3 channels are closed, and when high, they open for data sampling and transmission.

Before data is transmitted to G2/G3 gates, it passes through G4/G1 NAND gates, introducing a time delay. The concept of setup time is introduced to compensate for the delay at G4/G1 gates. That is, before the clock arrives, the input data at G2/G3 needs to be ready for correct sampling.

After data is sampled by the clock and before it is latched by the RS flip-flop, it also passes through G2/G3 gates, introducing a delay. Hold time is introduced to compensate for the delay at G2/G3 gates. That is, after the clock arrives, it ensures that data can be correctly transmitted to the input of G6/G5 NAND gates.

If data transmission does not meet setup or hold times, it will be in a metastable state, leading to transmission errors.

Constraint Conditions

Setup Time Constraint Condition

The figure below is a typical schematic of data transmission between flip-flops. "Comb" represents combinational logic delay, and "Clock Skew" represents clock skew, with data triggered at the rising edge of the clock.

Before the clock arrives, data needs to be prepared in advance to be correctly sampled by the clock, requiring the data path (data path) to be faster than the clock path (clock path), i.e., the data arrival time (data arrival time) to be less than the data required time (data required time). The expression for setup time to be satisfied is:

Tcq + Tcomb + Tsu <= Tclk + Tskew (1)

The time parameters are explained as follows:

Tcq: Delay from the clock input to the Q output of the register;
Tcomb: Combinational logic delay in the data path;
Tsu: Setup time;
Tclk: Clock period;
Tskew: Clock skew.

Transforming the above equation, the minimum clock period and the fastest clock frequency that the circuit can theoretically support are:

Minimum clock period = Tcq + Tcomb + Tsu - Tskew
Fastest clock frequency = 1 / (Tcq + Tcomb + Tsu - Tskew)

Hold Time Constraint Condition

After the clock arrives, data needs to remain stable for a period, which requires the data delay time (data delay time) of the previous stage not to be greater than the hold time of the flip-flop, to avoid data being flushed. The expression for hold time to be satisfied is:

Tcq + Tcomb >= Thd + Tskew (2)

The time parameters are explained as follows:

Tcq: Delay from the clock input to the Q output of the register;
Tcomb: Combinational logic delay in the data path;
Thd: Hold time;
Tskew: Clock skew.

From equations (1) and (2), the constraints on clock skew, combinational logic delay, and clock period can be derived.

It is recommended to remember only these two basic constraint condition expressions, and to derive other parameter constraints as needed to avoid confusion caused by various derivations.

Setup Time and Hold Time Timing Diagram

A complex timing diagram for setup and hold times is shown below.

Green represents the margin for setup time, and blue represents the margin for hold time. Time margin is essentially the difference between the times on both sides of inequality (1) or (2) under the condition of satisfying timing constraints.

Setup time margin = (clock path time) - (data path time)
Hold time margin = (data delay time) - (hold time + clock skew)

This diagram is just to help understand the derivation of setup and hold time constraint conditions. If it causes confusion, it is recommended not to delve into it (^_^).

Calculation Examples

To better understand the concepts of setup and hold times and to facilitate interviews or work, some typical setup and hold time problems are listed below for reference.

Example 1:

Considering network delay, the various delay values (in ns) of a circuit are as follows, with a clock period of 15ns. Please determine if the setup and hold times of this circuit have violations?

Solution:

This involves the maximum and minimum values of delay.

Since timing constraints must always hold, the transformations of equations (1) and (2) are:

max (data path time) <= min (clock path time)
min (data delay time) >= max (Thd + Tskew)

Setup time check:

max (data path time) = 2 + 11 + 2 + 9 + 2 + 2 = 28ns
min (clock path time) = 15 + 2 + 5 + 2 = 24ns

Therefore, there is a setup time violation.

Hold time check:

min (data delay time) = 1 + 9 + 1 + 6 + 1 = 18ns
max (Thd + Tskew) = 3 + 3 + 9 + 2 = 17ns

Therefore, there is no hold time violation, with a margin of 1ns.

This example cannot rigidly apply the expressions for setup and hold times; instead, constraints must be established from concepts such as data path, clock path, and data delay. Therefore, various timing constraint conditions must be analyzed according to the actual circuit.

Example 2:

A famous company interview question: The clock period is T, the maximum setup time of the first-stage flip-flop D1 is T1max, and the minimum is T1min. The maximum delay of combinational logic is T2max, and the minimum is T2min. What conditions should the setup and hold times of the second-stage flip-flop D2 satisfy?

Solution:

The setup and hold times of the second stage are not directly related to the first-stage flip-flop, so T1max and T1min are distracting items.

The example does not provide the delay from clock to Q or clock skew, so these do not need to be considered.

Following the guidance from Example 1, the setup time Tsu and hold time Thd of D2 should satisfy:

T2max + Tsu <= T
T2min >= Thold

That is,

Tsu <= T - T2max
Thold <= T2min

Many delay types are not considered in this example. When establishing timing constraint conditions, one needs to know what to omit based on the given conditions.

Example 3:

A simple frequency divider circuit is shown below. The setup time of the flip-flop is 3ns, the hold time is 3ns, the logic delay is 6ns, the delay of two inverters is 1ns, and the wiring delay is 0. What is the highest operating frequency of this circuit?

Solution:

The logic delay here should be understood as the delay from the clock input to the Q output, not the combinational logic delay in the circuit.

Since the Q output of the flip-flop is connected to the D input, it can be understood as direct transmission between two flip-flops, so there is no combinational logic delay in the data path, only an inverter delay.

Since there is only one clock, there is no clock skew, and the inverter delay in the clock path is a distracting item.

Therefore, the timing constraint condition is:

Tcq + Tbuf + Tsu <= Tclk

The highest operating frequency of the circuit is:

1 / (6ns + 1ns + 3ns) = 100Mhz.

This example is a feedback from the flip-flop to itself, and it is crucial to analyze the data path and clock path correctly. Let's look at another extended example of this type.

Example 4:

(1) What are the inherent setup and hold times of the following circuit?
(2) What is the highest operating frequency of this circuit?

Solution:

The circuit has delays in both the data path and the clock path, and to achieve the same setup and hold time constraints as the flip-flop, the timing diagram of the flip-flop D input and clock CK, as well as the equivalent data input Data and clock input Clock, is as follows (I've tried my best to make it concise~_~):

(1) From the diagram:

The inherent setup time of the circuit is: 2.1 + 2 - 1.2 = 2.9ns

The inherent hold time of the circuit is: 1.2 + 1.5 - 2.1 = 0.6ns

It can be seen that the delay in the data path increases the inherent setup time of the circuit but reduces the inherent hold time. Clock skew reduces the inherent setup time of the circuit but increases the inherent hold time.

Let me tell you a secret, calculating the inherent setup and hold times of the circuit is essentially the process of calculating time margins.

(2) This circuit is still a feedback from itself to itself. So there is no clock skew, and the delay T1= 0.9ns does not need to be considered. Therefore, the highest operating frequency is: 1 / (1.8 + 1.2 + 2)ns = 200MHz

-0.1 Digital Logic Design

-0.2 Verilog Coding Style

-0.3 Verilog Code Guide

-1.1 Verilog Gate Types

-1.2 Verilog Switch-Level Modeling

-1.3 Verilog Gate Delay

-2.1 Verilog UDP Basics

-2.2 Verilog Combinational Logic UDP

-2.3 Verilog Sequential Logic UDP

-3.1 Verilog Delay Models

-3.2 Verilog specify Block Statement