9.1 Verilog Logic Synthesis
Category Advanced Verilog Tutorial
This tutorial frequently mentions the term "synthesis." Some logic cannot be synthesized into actual circuits, or there may be security risks in the circuits after the synthesis of some logical designs. This chapter will briefly introduce the relevant knowledge of logic synthesis, only from a theoretical level and a general understanding perspective. When that naive young man becomes a bald middle-aged man, we will introduce the specific practice of logic synthesis. It seems there is not much time left (manually doge head).
Basic Concepts
Synthesis is the process of converting high-level descriptions of digital designs into optimized gate-level netlists based on standard cell libraries and specific design constraints. The standard cell library corresponds to the process library and can include simple basic logic gate units such as AND gates, NOT gates, and can also include special macro units, such as multipliers, special clock triggers, etc. Design constraints generally include constraints on timing, load, area, power consumption, and other aspects.
Whether it is digital chip design or FPGA development, the synthesis process is now basically done with the help of computer-aided logic synthesis tools, which automatically convert high-level descriptions into logic gate circuits. Designers can focus on system structure solutions, high-level descriptions, design constraints, and standard process libraries, without worrying about how high-level descriptions are converted into gate-level circuits. Synthesis tools repeatedly perform logic transformations and optimizations internally, ultimately generating the optimal gate-level circuit. The process is shown below.
Structural Interpretation
Simple assignment statements are usually synthesized into basic logic gate units.
assign F = (A & B) | C;
The above code is usually synthesized into the following gate-level circuit:
Conditional statements are usually synthesized into selectors.
assign F = sel ? A : B;
The above code is usually synthesized into the following gate-level circuit:
Assignment statements in always blocks triggered by clocks are usually synthesized into flip-flops.
always @(posedge clk) begin
q <= d;
end
The above code is usually synthesized into the following circuit:
No matter how complex the design is, after synthesis, it will be converted into a gate-level netlist composed of various unit library components. In short, logic synthesis can be narrowly understood as the process of converting Verilog designs into representations using optimized basic logic gate units and special macro units.
Synthesis Process
The detailed synthesis process from high-level RTL descriptions to gate-level netlists is shown in the figure below.
RTL Description
Design digital circuits using hardware description languages (such as Verilog) and simulate to ensure the correctness of logical functions.
Translation
The RTL description is converted by the synthesis tool into an unoptimized intermediate representation. This process reads the basic primitives and operations of the Verilog description, without considering design constraints such as area, timing, and power consumption, and only completes simple internal resource allocation.
Unoptimized Intermediate Representation
The intermediate representation generated during the translation process is recognized internally by the synthesis tool, and users do not need to understand it.
Logic Optimization
Optimize the design logic and remove redundant logic. This process often deletes or renames some variables in the RTL design, and the logic implementation process may also change to achieve the most optimized implementation of the logic. This process produces an optimized internal representation.
Process Mapping and Optimization
Before this step, the description process of the design is independent of the target process. In this step, the synthesis tool will use the logic units provided in the process library (standard cell library) to implement the internal representation of the design. That is, the design will be mapped to the target process. During the implementation process, it is also necessary to meet the constraints of timing, area, and power consumption, and perform some local optimizations.
Standard Cell Library
As previously mentioned, the standard cell library corresponds to the process library and can include simple basic logic gate units such as AND gates, NOT gates, and can also include special macro units, such as multipliers, special triggers, etc.
To better map and optimize, each logic unit should include the following information:
- Functional description
- Layout area
- Timing information
- Power consumption information
Design Constraints
Design constraints generally include constraints on timing, area, power consumption, and other aspects. There is often a trade-off relationship between the three. To optimize timing, it may be necessary to increase hardware resources, which leads to an increase in circuit area and power consumption. To produce a smaller circuit, it is necessary to compromise on circuit speed. Digital circuit design often requires a comprehensive consideration of various factors for trade-offs.
Optimized Gate-Level Representation
After the process mapping and optimization are completed, the final optimized gate-level netlist described by the target process library will be generated. If this