9.2 Verilog Synthesizable Design
Classification Advanced Verilog Tutorial
Verilog is primarily used for the description of digital circuit design, but not all descriptive methods can be synthesized into actual hardware circuits. For example, some keywords used for simulation verification belong to the simulation verification language and can only be used during simulation and cannot be synthesized into circuits, such as system tasks $display, initial statements, etc. Therefore, when using Verilog to design digital circuits, it is important to pay attention to the synthesizability of the circuit. Testbenches can be designed as desired, as long as they can construct the necessary simulation stimulus conditions.
Synthesizable and Non-Synthesizable Structures
Structures supported by all synthesis tools
| Structure Type | Keywords | Description |
|---|---|---|
| Port Signals | inout, input, output | There are only 3 types of port signals |
| Parameters | parameter, localparam | --- |
| Signal Variables | wire, reg, tri, integer | --- |
| Modules | module | --- |
| Gate Primitives | and, nand, or, nor, xor, xnor, buf, not, bufif0, bufif1, notif0, notif1, supply0, supply1 | Direct instantiation is possible |
| Instantiation | --- | Supports module instantiation, gate primitive instantiation, etc. |
| Functions and Tasks | function, task | Supports descriptions without timing structures |
| Continuous Assignment | assign | Does not support descriptions with delays |
| Procedural Assignment | always, begin, end | Can design sequential or combinational logic |
| Conditional Statements | if, case, default | Conditions cannot include comparisons with "z" or "x" |
| Loop Statements | for, while, forever | while, forever must contain @(posedge clk) or @(negedge clk), to avoid combinational logic loops |
| Edge Triggering | negedge, posedge | --- |
| Operators | --- | Supports all operators except "===" and "!==" |
Structures not supported by all synthesis tools
| Structure Type | Keywords | Description |
|---|---|---|
| Variable Types | time | Time variable used during simulation |
| System Tasks | --- | Most system tasks assist in simulation and cannot be synthesized into actual circuits <br> For example, $display, $fopen, $finish, etc. |
| Procedural Structures | initial | initial is often used for signal initialization during simulation <br> Or controlling the timing of stimulus signals |
| Parallel Statements | fork, join | Often used to describe parallel structures during simulation <br> Parallel structures described by always @(posedge clk) can be synthesized |
| Delay Statements | # | All descriptions with delay marker "#" are not synthesizable <br> But there will be delays in the circuit during simulation, and there will be no errors during synthesis |
| Level-Sensitive Triggering | wait | Often used for signal detection and startup in simulation |
| Force and Release Assignment | force, release | Often used to block other driving sources and force signal assignment during simulation |
Structures that synthesis tools may support
| Structure Type | Keywords | Description |
|---|---|---|
| x/z Conditional Statements | casex, casez | Some synthesis tools can recognize non-"x/z" comparison logic in the statement |
| Different Strength Nets | wand, triand, wor, trior | Needed when a signal has multiple driving sources <br> But these variable types are now basically abandoned in digital design |
| Real Variables | real | Often used for precise calculations during simulation |
| Process Termination | disable | Terminates the execution of a process block, most synthesis tools do not support this command |
| Loop Statements | repeat, while, forever | repeat is often used for fixed number of iterations in simulation <br> while, forever may also be synthesizable when the number of iterations is a constant |
| User-Defined Primitives | UDP | In fact, most synthesis tools currently support UDP <br> It's just that some older synthesis tools will not recognize it |
| Procedural Continuous Assignment | assign, deassign | Tools mostly do not support the synthesis of reg data type under this operation <br> Support the synthesis of wire data type under this operation |
Synthesizable Design Recommendations
When using Verilog for digital design, the following principles should be followed: boldly use synthesizable structures, use non-synthesizable structures in simulation, and try not to use structures that some synthesis tools support and some do not.
Unless for some special designs, such as clkgate, clock switching, and other circuits, do not write logic that may potentially be synthesized into Latches. For details, see the section "6.5 Avoiding Latches in Verilog" in the