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2.2 Verilog Numerical Representation

Category Verilog Tutorial

Types of Values

Verilog HDL has the following four basic values to represent the logic levels in hardware circuits:

x indicates an uncertain signal value, meaning the signal could be 1 or 0 in the actual circuit.

z indicates a high impedance state, commonly seen when a signal (input, reg) is not driven. For example, when an input of a pad is in a high impedance state, its logical value depends on the pull-up or pull-down state. Pull-up results in a logical value of 1, and pull-down results in 0.

Integer Representation Methods

When declaring numbers, there are four valid base formats: decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or 'B), and octal ('o or 'O). The bit width can be specified or not.

Specifying Bit Width:

Example

4'b1011          // 4-bit value
32'h3022_c0de    // 32-bit value

The underscore _ is used to enhance code readability.

Not Specifying Bit Width:

When writing numbers directly, the default is decimal representation. The following three ways are equivalent:

Example

counter = 'd100 ; // Usually allocated based on the compiler, commonly 32-bit
counter = 100 ;
counter = 32'h64 ;

Negative Number Representation:

A negative sign is typically added before the bit width to represent negative numbers. For example:

-6'd15  
-15

-15 in 5-bit binary is 5'b10001, and in 6-bit binary is 6'b11_0001.

Note that placing the negative sign between the base and the number is illegal, such as in the following incorrect representation:

4'd-2 // Illegal notation

Real Number Representation Methods

There are mainly two ways to represent real numbers:

Decimal:

30.123
6.0
3.0
0.001

Scientific Notation:

1.2e4         // Equals 12000
1_0001e4      // Equals 100010000
1E-3          // Equals 0.001

String Representation Methods

A string is a sequence of characters enclosed in double quotes. Strings cannot be written across multiple lines, meaning they cannot include a carriage return. Verilog treats strings as a series of single-byte ASCII characters. For example, to store the string "www.tutorialpro.org", 14*8-bit storage units are needed. For example:

Example

reg [0: 14*8-1]       str ;
initial begin
    str = "www.tutorialpro.org";
end

-1.1 Verilog Tutorial

-1.2 Verilog Introduction

-1.3 Verilog Environment Setup

-1.4 Verilog Design Methods

-2.1 Verilog Basic Syntax

-2.3 Verilog Data Types

-2.4 Verilog Expressions

-2.5 Verilog Compile Instructions

-3.1 Verilog Continuous Assignment

-3.2 Verilog Time Delay

-4.1 Verilog Process Structure

-4.2 Verilog Process Assignment

-4.3 Verilog Timing Control

-4.4 Verilog Statement Blocks

-4.5 Verilog Conditional Statements

-4.6 Verilog Case Statements

-4.7 Verilog Loop Statements

-4.8 Verilog Procedural Continuous Assignment

-5.1 Verilog Modules and Ports

-5.2 Verilog Module Instantiation

-5.3 Verilog Parameterized Instantiation

-6.1 Verilog Functions

-6.2 Verilog Tasks

-6.3 Verilog State Machines

-6.4 Verilog Race and Hazard

-6.5 Verilog Avoiding Latch

-6.6 Verilog Simulation Stimulus

-6.7 Verilog Pipelining

-7.1 Verilog Divider Design

-7.2 Verilog Parallel FIR Filter Design

-7.3 Verilog Serial FIR Filter Design

-7.4 Verilog CIC Filter Design

-7.5 Verilog FFT Design

-7.6 Verilog DDS Design

-8.1 Verilog Numerical Conversion

-Verilog Advanced Tutorial

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