6.1 Introduction to Low Power in Verilog
Category Advanced Verilog Tutorial
Keywords: Switching Power, Internal Power, Static Power
Impact of Power Consumption
Portability
The lower the power consumption, the longer the working time of electronic products under the same battery capacity, and the difficulty of designing the battery capacity and volume of portable devices will also be reduced. For example, the increasingly thinner design of mobile phones without affecting performance is due to the crucial role played by low power design.
Performance
The greater the power consumption, the more energy is consumed, the more heat is generated, and the performance of various devices will be affected. For example, when using a mobile phone for a long time, the phone will feel hot, and various applications may also experience lag.
Cost
When low power design is not considered, the implementation method of a function may be more cumbersome, the number of devices increases, and the product area increases; at the same time, when the power consumption is too high, cooling devices must be considered, which increases the assembly cost. In short, low power design has many advantages and is also the development trend of digital design in the future.
Types of Power Consumption
Power consumption can generally be divided into dynamic power, static power, and surge power.
Dynamic Power
Dynamic power mainly includes switching power (also known as toggle power) and short-circuit power (also known as internal power).
1. Switching Power
In CMOS digital circuits, the power consumed when charging and discharging the load capacitance is switching power. As shown in the following CMOS NOT gate:
When Vin = 0, the PMOS above is on, the NMOS below is off; VDD charges the load capacitance Cload. After charging, the level of Vout is high.
When Vin = 1, the PMOS above is off, the NMOS below is on, and the load capacitance discharges through the NMOS. After discharging, the level of Vout is low.
This on-and-off change, that is, the charging and discharging of the power supply, forms the switching power. The formula for calculating switching power is as follows:
Where VDD is the supply voltage, Cload is the equivalent load capacitance of the subsequent circuit, and Tr is the toggle rate of the input signal.
2. Short-Circuit Power
The toggle of a signal is not instantaneous. Therefore, when the input signal toggles, there is always a period when the PMOS and NMOS are both on, forming a path from the power supply VDD to the ground VSS, creating a short-circuit current and generating short-circuit power. As shown in the following inverter circuit diagram:
The formula for calculating short-circuit power is as follows:
Where Vdd is the supply voltage, Tr is the toggle rate, and Q is the charge that flows from the power supply to the ground during one toggle.
Static Power
In CMOS circuits, static power consumption is mainly caused by leakage current, which is often related to the process.
The composition of leakage current mainly includes: PN junction reverse current I1, sub-threshold leakage current I2 between the source and drain, gate leakage current (including the induced leakage current I3 between the gate and drain), and the tunnel leakage current I4 between the gate and substrate.
In general, leakage current mainly refers to gate leakage current and sub-threshold current. For ultra-deep sub-micron processes, tunnel leakage current becomes one of the main currents.
- When a reverse voltage is applied to the ends of a PN junction, the movement of holes in the P region and electrons in the N region is opposite, and no current passes through, the diode is in the off state, and some high-energy holes and electrons will break free from the reverse electric field and form a weak drift current.
- Gate leakage power: After a signal is applied to the gate (i.e., gate voltage), there is a capacitance between the gate and substrate, so there will be a current between the gate and substrate, which will result in power consumption.
- Sub-threshold current: When the gate voltage is below the conduction threshold, leakage current will still be generated from the drain to the source. This current is called sub-threshold leakage current. In narrower transistors, where the distance between the drain and source is close, sub-threshold leakage current will be generated. The narrower the transistor, the greater the leakage current. To reduce sub-threshold current, high-threshold devices can be used, and the threshold voltage can be increased by substrate bias, which also belongs to the consideration of low power design.
- Tunnel leakage current: It belongs to the field of value: 0.048082; when: "!A1 !A2 !Z"; related_pg_pin: VDD; }
leakage_power() { value: 0.053318; when: "!A1 A2 !Z"; related_pg_pin: VDD; } ……
Static power consumption is related to the state of the cell, meaning that power consumption will vary with different input and output signal states. By looking up the state, the corresponding static power consumption can be obtained. When analyzing power consumption in practice, one would not manually search for relevant parameters to calculate power consumption, as the workload would be too immense to estimate. It is often done with the help of some power analysis tools, extracting power consumption information from these standard cell libraries for integrated calculation.
6.1 Introduction to Low Power in Verilog