7.4 Verilog CIC Filter Design
Category Verilog Tutorial
Cascaded Integrator-Comb (CIC) filters are commonly used in Digital Down Converter (DDC) and Digital Up Converter (DUC) systems. The CIC filter has a simple structure, with no multipliers, only adders, integrators, and registers. It consumes few resources and operates at high speeds, capable of high-speed filtering. It is often used in the first stage with the highest input sampling rate and is widely used in multi-rate signal processing systems.
DDC Principle
DDC Working Principle
The DDC mainly consists of a Numerically Controlled Oscillator (NCO), mixer, and filter, as shown in the figure below.
The DDC mixes the intermediate frequency signal with the carrier signal generated by the oscillator, the signal's central frequency is shifted, and then it passes through a decimation filter to restore the original signal, achieving the down-conversion function.
When sampling intermediate frequency data, a very high sampling frequency is required to ensure that the ADC (Analog-to-Digital Converter) captures the signal's signal-to-noise ratio. After digital down-conversion, the obtained baseband signal's sampling frequency is still the ADC sampling frequency, so the data rate is very high. At this time, the effective bandwidth of the baseband signal is often much less than the sampling frequency. Therefore, using decimation and filtering to convert the data rate, reducing the sampling rate to avoid resource waste and design difficulties, has become an indispensable part of the DDC.
Using the CIC filter for data processing is the most common method for the decimation filtering part of the DDC.
Bandpass Sampling Theorem
In the DDC system, the input intermediate frequency carrier signal will be frequency-shifted according to the carrier frequency to obtain a bandpass signal. If the Nyquist sampling theorem is still used at this time, that is, the sampling frequency is twice the highest frequency of the bandpass signal, then the required sampling frequency will be very high, and the design will become complex. At this time, the bandpass sampling theorem can be used to determine the sampling frequency.
Bandpass Sampling Theorem: A signal with a frequency band limited to
can be completely reconstructed without distortion from its sample values.
When m=1, the bandpass sampling theorem is the Nyquist sampling theorem.
Another way to describe the bandpass sampling theorem is: if the highest frequency of the signal is an integer multiple of the signal bandwidth, the sampling frequency only needs to be greater than twice the signal bandwidth, and aliasing will not occur.
Therefore, it can be considered that half of the sampling frequency is the cutoff frequency of the CIC filter.
DDC Frequency Shift
For example, a bandwidth signal with a central frequency of 60MHz and a bandwidth of 8MHz has a frequency range of 56MHz to 64MHz, and the range of m values is 0 to 7. Take m=1, then the sampling frequency range is 64MHz to 112MHz.
Take the sampling frequency as 80MHz, set the NCO central frequency to 20MHz, and discuss the complex signal frequency spectrum shift schematic.
(1) Considering the symmetry of the spectrum, the frequency spectrum diagram of the input complex signal is as follows:
(2) After sampling at a sampling frequency of 80MHz, the 56~64MHz frequency band is shifted to the -24~-16MHz and 136~144MHz (filtered out above the sampling frequency) frequency bands, and the -64~-56MHz frequency band is shifted to the -144~-136MHz (filtered out above the sampling frequency) and 16~24MHz frequency bands.
The frequency band distribution after sampling is as follows:
(3) After the signal passes through the 20MHz NCO's orthogonal circuit, the -24~-16MHz frequency band is shifted to the -4~4MHz and -44~-36MHz frequency bands, and the 16~24MHz frequency band is shifted to the -4~4MHz and 36~44MHz frequency bands, as shown below.
(4) At this time, the intermediate frequency input signal has been shifted to the zero intermediate frequency baseband.
The bandwidth signal of -44~-36MHz and 36~44MHz is not needed and can be filtered out; the zero intermediate frequency signal data rate of -4~4MHz is still 80MHz, and decimation can be performed to reduce the data rate. And the CIC filter is to complete this process.
The above review has covered a lot of digital signal processing content, just as a brick to DDC, to lead to the jade of CIC.
CIC Filter Principle
Single-stage CIC Filter
Assume the if (!rstn) begin valid_r <= 1'b0; dout_r <= 'b0; end else if (en) begin if (cnt==4) begin valid_r <= 1'b1; dout_r <= din; end else begin valid_r <= 1'b0; end end end
assign dout = dout_r; assign valid = valid_r;
endmodule
Comb Filter Design
A comb filter is a simple first-order FIR filter. Each stage of the FIR filter delays the data by one clock cycle and then subtracts it. Since the coefficients are ±1, no multiplier is needed.
Example
module comb
#(parameter NIN = 21,
parameter NOUT = 17)
(
input clk,
input rstn,
input en,
input [NIN-1:0] din,
input valid,
output [NOUT-1:0] dout);
//en delay
reg [5:0] en_r;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
en_r <= 'b0;
end else if (en) begin
en_r <= {en_r[4:0], en};
end
end
reg [NOUT-1:0] d1, d1_d, d2, d2_d, d3, d3_d;
//stage 1, as fir filter, shift and add(sub),
//no need for multiplier
always @(posedge clk or negedge rstn) begin
if (!rstn) d1 <= 'b0;
else if (en) d1 <= din;
end
always @(posedge clk or negedge rstn) begin
if (!rstn) d1_d <= 'b0;
else if (en) d1_d <= d1;
end
wire [NOUT-1:0] s1_out = d1 - d1_d;
//stage 2
always @(posedge clk or negedge rstn) begin
if (!rstn) d2 <= 'b0;
else if (en) d2 <= s1_out;
end
always @(posedge clk or negedge rstn) begin
if (!rstn) d2_d <= 'b0;
else if (en) d2_d <= d2;
end
wire [NOUT-1:0] s2_out = d2 - d2_d;
//stage 3
always @(posedge clk or negedge rstn) begin
if (!rstn) d3 <= 'b0;
else if (en) d3 <= s2_out;
end
always @(posedge clk or negedge rstn) begin
if (!rstn) d3_d <= 'b0;
else if (en) d3_d <= d3;
end
wire [NOUT-1:0] s3_out = d3 - d3_d;
//tap the output data for better display
reg [NOUT-1:0] dout_r;
reg valid_r;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
dout_r <= 'b0;
valid_r <= 'b0;
end else if (en) begin
dout_r <= s3_out;
valid_r <= 1'b1;
end else begin
valid_r <= 1'b0;
end
end
assign dout = dout_r;
assign valid = valid_r;
endmodule
Top-Level Instantiation
By instantiating the integrator, decimator, and comb filter according to the signal flow, the final CIC filter module can be formed.
The final output bit width of the comb filter is generally smaller than the input signal, and here it is taken as 17 bits. Of course, the output bit width can be consistent with the bit width of the input data.
Example
``` module cic #(parameter NIN = 12, parameter NMAX = 21, parameter NOUT = 17) ( input clk, input rstn, input en, input [NIN-1:0] din, input valid, output [NOUT-1:0] dout);
wire [NMAX-1:0
Simulation Results
As shown in the simulation results below, the signal after passing through the CIC filter only contains a low-frequency signal (250KHz), and the high-frequency signal (7.5MHz) has been filtered out.
However, the waveform is not very perfect, which is related to the designed cutoff frequency, the data is not continuously output, and so on.
At this time, it is found that the data signal output by the integrator is also very irregular, which is related to its bit width.
In order to better observe the data output of the integrator, its bit width is changed from 21 bits to 34 bits, and the simulation results are as follows.
At this time, it is found that there is no substantial change in the data output of the CIC filter, but the data signal output by the integrator shows a sawtooth shape, also known as a comb shape. This is also the origin of the name comb filter.
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7.4 Verilog CIC Filter Design