1.3 Setting Up the Verilog Environment

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1.3 Setting Up the Verilog Environment

Category Verilog Tutorial

When learning Verilog for simulation, you can choose from different simulation environments. FPGA development environments include Xilinx's ISE (now discontinued), VIVADO; Intel's Quartus II; ASIC development environments include Synopsys' VCS; many also use Icarus Verilog and GTKwave for a more lightweight approach.

Although ISE or Quartus II come with their own simulators, they are still lacking in functionality. Therefore, this guide introduces the joint simulation testing method using Quartus II + Modelsim, running on a 64bit-win10 system.

Quartus II Installation

This guide uses Quartus version 10.1.

Currently, the official Quartus II website no longer provides installation packages for versions below 13.1. You can install software versions above 13.1. The functions are largely similar. Download link: https://fpgasoftware.intel.com/13.1/?edition=subscription&platform=windows

When downloading Quartus II above version 13.1, the official website will also recommend the corresponding version of Modelsim, which can be downloaded together.

Start the installation, modify the installation path, and follow the default settings step by step.

The screenshot below shows a successful installation.

If a License file is required, as shown in the figure, you need to specify the license file purchased with the software.

If the license file needs to replace the Host-ID, simply replace the HOSTID in the license file with any ID from the NIC options, as shown in the red box below:

After installing Quartus II 10.1, you also need to install Device, which installs the library files supporting various programmable logic device models, otherwise Quartus II cannot properly establish a project.

The installation path needs to be selected as the Quartus II installation path, where Device installation can automatically recognize Quartus II.

The latest Quartus II (e.g., the 2016 version) already supports integrated installation.

Modelsim Installation

Choose the modelsim-win64-10.1c-se version.

You also need to modify the installation path, then follow the default settings to proceed.

After installation, you may be prompted to restart the computer, just restart it.

Establishing a Quartus II Project

Create Project

File -> New project Wizard

Set the working path, project name, and top module name.

Note that the path and name settings must not contain Chinese characters.

Select Device Model

We are only conducting simple simulations and not downloading or burning, so we do not need to care about specific signals, just choose any one.

Then click Next until Finish.

Create a New Verilog Source File

Below is a simple simulation of a 4-bit wide decimal counter.

Click: File -> New -> Verilog HDL File -> OK

Click: File -> Save As

Enter the module name: counter10.v

It should be noted that the top module name must be consistent with the project name, otherwise an error will be reported (as shown in the figure).

Copy the Verilog code into the file counter10.v and perform a one-click compilation (which actually includes compilation, synthesis, placement, and routing).

When an error occurs, you can click on the Error log to locate the error and make corrections until there are no errors.

Quartus II Calling Modelsim for Simulation

Set the simulator to Modelsim-altera

Click: Tool -> Options -> EDA Tool Options

Change the address after Modelsim to the path of the Modelsim startup program.

Select the Simulator

Click: Assignments -> Simulation

Select ModelSim in Tool name and set Format, Time scale, etc., as shown.

Write the testbench File

Click: Processing -> start -> Start TestBench Template Writer

If set correctly, a .vt file will be generated in the project path simulation/modelsim.

The .vt file template already provides code for the port section, interface variable declarations, and instantiation statement mappings. We need to fill in the test code in the appropriate position in the testbench.

Here, write a simple clock and reset drive code, as shown in the figure below.

Add the testbench to the Project

Click: Assignments -> Settings -> Simulation

In the Compile test bench option, select new, set the Test bench name, and add the .vt file generated in the previous step to the project via File name search.

It should be noted that the testbench file name needs to be consistent with the top module name in the testbench, otherwise an error will be reported when starting Modelsim, preventing normal simulation.

Recompile with One Click

At this time, you will find that the compilation status in the Tasks column has become a question mark, requiring a one-click recompile.

Call Modelsim for Simulation

Click: Tools -> Run simulation Tool -> RTL Simulation

This will automatically start the Modelsim software.

The operation of Modelsim is not specifically introduced here.

From the simulation diagram, it can be seen that our design has completed the basic function of decimal counting.

Summary

In my memory, the joint simulation function of Quartus II + Modelsim is powerful and easy to install. After a few years, I went through this process again and found that the steps were a bit cumbersome, taking me an entire evening to figure out. Many details are also mentioned above, just pay attention to them. However, when you have the opportunity to conduct large-scale digital module simulations in the future, you will find the effectiveness of this method.

In the following tutorials, some simple simulations may be done using other software, and the screenshot interfaces may differ from Modelsim. Do not doubt the accuracy of the simulation when you see them, this is specifically noted.

The design module and testbench source code will also be fully provided, allowing you to simulate and verify on your own.

-1.1 Verilog Tutorial

-1.2 Verilog Introduction