4.6 Verilog Multi-branch Statement

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4.6 Verilog Multi-branch Statement

Category Verilog Tutorial

Keywords: case, selector

The case statement is a form of multi-condition branch that addresses the inconvenience of using an if statement with multiple condition options.

Case Statement

The format of the case statement is as follows:

case(case_expr)
    condition1     :             true_statement1 ;
    condition2     :             true_statement2 ;
    ……
    default        :             default_statement ;
endcase

When the case statement is executed, if condition1 is true, true_statement1 is executed; if condition1 is false and condition2 is true, true_statement2 is executed; and so on. If none of the conditions are true, the default_statement is executed.

The default statement is optional and there cannot be multiple default statements in a single case statement.

There can be multiple condition options, not limited to condition1, condition2, etc., and these condition options do not need to be mutually exclusive. Although these condition options are compared concurrently, the execution effect is that the first true condition is executed.

The true_statement1 and similar execution statements can be a single statement or multiple statements. If there are multiple execution statements, they need to be enclosed with begin and end keywords.

The case statement supports nested use.

Below is an example of using a case statement to replace an if statement to implement a 4-way selector function. The simulation results and testbench can be referenced in the Conditional Statement chapter, which are identical.

Example

module mux4to1(
    input [1:0]     sel ,
    input [1:0]     p0 ,
    input [1:0]     p1 ,
    input [1:0]     p2 ,
    input [1:0]     p3 ,
    output [1:0]    sout);

    reg [1:0]       sout_t ;
    always @(*)
        case(sel)
            2'b00:    begin       
                        sout_t = p0 ;
                    end
            2'b01:        sout_t = p1 ;
            2'b10:        sout_t = p2 ;
            default:      sout_t = p3 ;
        endcase
    assign sout = sout_t ;

endmodule

The condition options in the case statement do not have to be constants; they can also be x or z values.

When multiple condition options need to execute the same statement, these options can be separated by commas and placed in the same statement block.

However, the comparison logic for x or z in the case statement is not synthesizable, so it is generally not recommended to use x or z as comparison values in the case statement.

For example, extending the case statement for a 4-way selector is shown below:

Example

case(sel)
    2'b00:    sout_t = p0 ;
    2'b01:    sout_t = p1 ;
    2'b10:    sout_t = p2 ;
    2'b11:      sout_t = p3 ;
    2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx :
        sout_t = 2'bxx ;
    2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z :
        sout_t = 2'bzz ;
    default:  $display("Unexpected input control!!!");
endcase

Casex/Casez Statements

casex and casez are variations of the case statement used to represent don't-care items in the condition options.

casex uses "x" to denote don't-care values, and casez uses a question mark "?" to denote don't-care values.

Both serve the same function, and their syntax is identical to that of the case statement.

However, casex and casez are generally not synthesizable and are mostly used in simulations.

For example, using the casez statement to implement a 4-bit control terminal 4-way selector:

Example

module mux4to1(
    input [3:0]     sel ,
    input [1:0]     p0 ,
    input [1:0]     p1 ,
    input [1:0]     p2 ,
    input [1:0]     p3 ,
    output [1:0]    sout);

    reg [1:0]       sout_t ;
    always @(*)
        casez(sel)
            4'b???1:     sout_t = p0 ;
            4'b??1?:     sout_t = p1 ;
            4'b?1??:     sout_t = p2 ;
            4'b1???:     sout_t = p3 ;  
        default:         sout_t = 2'b0 ;
    endcase
    assign      sout = sout_t ;

endmodule