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❮ 15 Sorting Algorithms Visually Displayed Verilog2 Udp Timing ❯

4.1 Verilog Synchronization and Asynchrony

Category Advanced Verilog Tutorial

Keywords: Synchronization, Asynchrony

As can be seen from Chapter 3, when the data at the input of a flip-flop and the clock of the flip-flop are unrelated, it is easy to cause the circuit timing to be unsatisfied. This chapter mainly addresses the asynchronous issues between modules that can lead to timing violations.

There are many places that introduce the definition of asynchronous and synchronous, and there are also some differences in details. The focus of this chapter is the method to solve the asynchronous problem, rather than why asynchronous clocks appear, nor the specific structure of the asynchronous circuit, only from the timing results of the asynchronous clock to analyze and solve the problem.

Synchronous Clock

In digital design, it is generally believed that two clocks with the same frequency or an integer multiple of the frequency ratio, and the same phase or a fixed phase difference, are considered synchronous clocks.

Or it can be understood that two clocks with the same source and an integer multiple of the frequency ratio are synchronous clocks. In fact, the same source of the clock ensures the fixedness of the phase difference. It can be specifically classified as follows:

Same Source, Same Frequency, Same Phase

Such clocks have the same frequency and phase, which are synchronous. Data transmission between clocks only needs to meet the normal setup time and hold time, without the need for special synchronous design.

Same Source, Same Frequency, Different Phases

When two clocks have the same frequency but different phases, as long as the phase difference remains fixed, they can also be considered synchronous. Because as long as the data delay between the two clocks is controlled within a reasonable range, it will not lead to timing issues. Moreover, the fixed clock delay can also be repaired at the floorplan level.

A fixed phase difference can be understood as the offset caused by different paths between two clocks under the same source clock.

Same Source, Different Frequencies but with an Integer Multiple Frequency Ratio

In this case, one clock is often a frequency division of another clock, and even if there is a phase difference, it is fixed.

When a single-bit signal is transmitted from the slow clock domain to the fast clock domain, because it is of the same source, as long as the setup time and hold time are met, the fast clock domain will always capture the signal transmitted from the slow clock domain.

As shown in the figure below, the rising edge of clk2 can always capture the signal sig1 from the clk1 domain, and the high level duration of the captured signal sig2 is also the frequency ratio of the two clocks, that is, 2 cycles.

If the signal sig2 in the clk2 domain only needs to last for one clock cycle, then the rising edge detection of sig1 is required.

Example

The Verilog description of the rising edge detection program between synchronous signals is as follows.</p>    reg [1:0]    sig2_r ;    always @(posedge clk2 or negedge rstn) begin      if (!rstn) sig2_r  <= 2'b0 ;      else       sig2_r  <= {sig2_r[0], sig1} ;    end    assign sig2 = sig2_r[0] && !sig2_r[1];

The simulation result is shown in the figure below.

When a single-bit signal is transmitted from the fast clock domain to the slow clock domain, as long as the slow clock domain can safely capture the signal transmitted from the fast clock domain, there is no asynchronous problem. Because the two clocks are of the same source. As shown in the figure below, the transmission from sig1 to sig2.

However, if the signal in the fast clock domain is too narrow, the slow clock domain may miss the signal, as shown in the transmission from sig11 to sig22 in the figure below. At this time, it is necessary to widen the narrow pulse signal in the fast clock domain.

When the frequency ratio of the two clocks is relatively small, the signal can be widened by delaying the signal in the fast clock domain;

When the frequency ratio of the two clocks is quite different, the effective time of the single-bit signal can be extended by using a counting method in the fast clock domain.

The Verilog description of using delay to widen the narrow pulse signal is as follows. Since the frequency ratio of clk1 and clk2 is 2, it only needs to be delayed by 2 beats in the clk2 clock domain.

Example

``` reg [1:0]    sig11_r ;    always @(posedge clk1 or negedge rstn) begin      if (!rstn) sig11_r  <

❮ 15 Sorting Algorithms Visually Displayed Verilog2 Udp Timing ❯