5.1 Introduction to Verilog Reset

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5.1 Introduction to Verilog Reset

Category Advanced Verilog Tutorial

Keywords: Synchronous Reset, Asynchronous Reset

To ensure that the system has a clear and stable initial state after power-up, or to restore the system to a normal initial state when the operating state becomes chaotic, a reset circuit module is essential in digital system design. An abnormal reset circuit can lead to functional anomalies in the entire system, so to some extent, the importance of the reset circuit is no less than that of the clock circuit.

Reset circuits can be classified into synchronous reset and asynchronous reset.

Synchronous Reset

A synchronous reset means that the reset signal is effective when the clock's active edge arrives. Without a clock, no matter how the reset signal changes, the circuit does not perform a reset operation.

The typical code description for a synchronous reset is as follows:

Example

module sync_reset(
    input       rstn,  // Synchronous reset signal
    input       clk,   // Clock
    input       din,   // Input data
    output reg  dout   // Output data
    );

    always @(posedge clk) begin   // Do not include the reset signal in the sensitivity list
        if(!rstn)  dout <= 1'b0 ; // rstn signal is synchronized with clock clk
        else       dout <= din ;
    end

endmodule

This description code is often synthesized into the following circuit:

Synchronous reset advantages: Signals are synchronized, can filter out glitches in the reset signal, and is beneficial for timing analysis.

Synchronous reset disadvantages: Most flip-flop units do not have synchronous reset terminals, so using synchronous reset consumes additional logic resources. The width of the reset signal must be greater than one clock cycle, otherwise, the reset signal might be missed.

Asynchronous Reset

An asynchronous reset means that the circuit performs a reset operation whenever the reset signal is effective, regardless of whether the clock is present or not.

The typical code description for an asynchronous reset is as follows:

Example

module async_reset(
    input       rstn,  // Asynchronous reset signal
    input       clk,   // Clock
    input       din,   // Input data
    output reg  dout   // Output data
    );

    // Reset signal must be included in the sensitivity list
    always @(posedge clk or negedge rstn) begin
        if(!rstn)  dout <= 1'b0 ; // rstn signal is asynchronous with clock clk
        else       dout <= din ;
    end

endmodule

This code is often synthesized into the following circuit:

Asynchronous reset advantages: Most flip-flop units have asynchronous reset terminals, so it does not consume extra logic resources. The asynchronous reset signal is directly referenced without processing, making the design simpler and signal recognition faster and more convenient.

Asynchronous reset disadvantages: The reset signal has no definite timing relationship with the clock signal, and asynchronous reset can easily cause timing violations in removal and recovery. It is also susceptible to glitches, potentially leading to unintended reset operations.

Asynchronous Reset, Synchronous Release

Considering design and resource aspects, asynchronous reset is generally used in digital system design.

To eliminate the drawbacks of asynchronous reset, the reset circuit often employs the "asynchronous reset, synchronous release" design method. This means that the reset signal arrives without being synchronized by the clock signal, but the release of the reset signal requires synchronization with the clock signal.

The typical code description for asynchronous reset, synchronous release is as follows:

Example

module areset_srelease(
    input       rstn,  // Asynchronous reset signal
    input       clk,   // Clock
    input       din,   // Input data
    output reg  dout   // Output data
    );

    reg   rstn_r1, rstn_r2;
    always @ (posedge clk or negedge rstn) begin
        if (!rstn) begin
            rstn_r1 <= 1'b0;     // Asynchronous reset
            rstn_r2 <= 1'b0;  
        end
        else begin
            rstn_r1 <= 1'b1;     // Synchronous release
            rstn_r2 <= rstn_r1;  // Synchronize and delay, additional delays can be added if needed
        end
    end

    // Use rstn_r2 for synchronous reset, reset signal can be included in the sensitivity list
    always @ (posedge clk or negedge rstn_r2) begin
        if (!rstn_r2) dout <= 1'b0; // Synchronous reset
        else          dout <= din;
    end

endmodule

This code description is often synthesized into the following circuit:

It should be noted that the reset circuit consumes more hardware logic and area resources, increasing the complexity of system design. Flip-flops without reset terminals also have relatively high performance. Therefore, in some digital designs where the initial value does not affect logical correctness, such as some data processing parts in the data path, or some registers in high-speed pipelines, it may be considered to remove the reset for optimal performance.

For convenience and quick simulation of other non-reset logic functions, the reset in all digital designs in the tutorial is introduced asynchronously from the testbench, without considering the timing issues of the reset circuit. When designing a digital system in practice, the reset circuit must be designed separately, carefully, and cautiously.

-0.1 Digital Logic Design

-0.2 Verilog Coding Style

-0.3 Verilog Code Specification

-1.1 Verilog Gate Types

-1.2 Verilog Switch-Level Modeling

-1.3 Verilog Gate Delay

-2.1 Verilog UDP Basics

-2.2 Verilog Combinational Logic UDP

-2.3 Verilog Sequential Logic UDP

-3.1 Verilog Delay Models

-3.2 Verilog specify Block Statements

-3.3 Verilog Setup and Hold Time