7.2 Verilog Parallel FIR Filter Design
Category Verilog Tutorial
FIR (Finite Impulse Response) filters are filters with finite-length unit impulse responses, also known as non-recursive filters.
FIR filters have strict linear phase-frequency characteristics, and their unit responses are of finite length, making them stable systems, widely used in digital communication, image processing, and other fields.
Principle of FIR Filters
FIR filters are finite-length unit impulse response filters. The direct structure is as follows:
The essence of an FIR filter is the convolution of the input signal with the unit impulse response function, expressed as follows:
FIR filters have the following characteristics:
(1) The response is a finite-length sequence.
(2) The system function converges at |z| > 0, with all poles at z=0, belonging to a causal system.
(3) Structurally, it is non-recursive, with no feedback from output to input.
(4) The phase response to the input signal is linear because the response function h(n) coefficients are symmetric.
(5) The relative phase difference between various frequencies of the input signal is also fixed.
(6) The convolution in the time domain is equivalent to multiplication in the frequency domain, so this convolution is equivalent to selecting the gain of each frequency component in the spectrum. Some frequency components are retained, and some are attenuated, thereby achieving the effect of filtering.
Parallel FIR Filter Design
Design Description
The input frequency is a mixed signal of 7.5 MHz and 250 KHz sine waves. After passing through the FIR filter, the high-frequency signal of 7.5MHz is filtered out, leaving only the 250KHz signal. The design parameters are as follows:
Input Frequencies: 7.5MHz and 250KHz
Sampling Frequency: 50MHz
Stop Band: 1MHz to 6MHz
Order: 15 (N-1=15)
From the structure of the FIR filter, it can be seen that when the order is 15, the implementation of the FIR requires 16 multipliers, 15 adders, and 15 sets of delay registers. To stabilize the data of the first beat, an additional set of delay registers can be used, totaling 16 sets of delay registers. Due to the symmetry of the FIR filter coefficients, the number of multipliers can be halved, using a total of 8 multipliers.
Parallel design means that within a clock cycle, 16 sets of delayed data are simultaneously subjected to multiplication and addition operations, and then the filtered value is output under the clock drive. The advantage of this method is short filtering delay, but it has high requirements for timing.
Parallel Design
The multiplier module code used in the design can refer to the multiplier in the previously designed pipeline.
For convenient and fast simulation, the multiplication operation can also be directly completed using the multiplication sign *, and the macro definition SAFE_DESIGN is added to the design to choose which multiplier to use.
The FIR filter coefficients can be generated by matlab, see the appendix for details.
Example
/***********************************************************
>> V201001 : Fs: 50MHz, fstop: 1MHz-6MHz, order: 15
************************************************************/
`define SAFE_DESIGN
module fir_guide(
input rstn, //Reset, active low
input clk, //Operating frequency, i.e., sampling frequency
input en, //Input data valid signal
input [11:0] xin, //Input mixed frequency signal data
output valid, //Output data valid signal
output [28:0] yout //Output data, low-frequency signal, i.e., 250KHz
);
//Data en delay
reg [3:0] en_r;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
en_r[3:0] <= 'b0;
end
else begin
en_r[3:0] <= {en_r[2:0], en};
end
end
//(1) 16 sets of shift registers
reg [11:0] xin_reg[15:0];
reg [3:0] i, j;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (i=0; i<15; i=i+1) begin
xin_reg[i] <= 12'b0;
end
end
else if (en) begin
xin_reg[0] <= xin;
for (j=0; j<15; j=j+1) begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
sum <= 29'd0;
yout_t <= 29'd0;
end
else if (valid_mult7) begin
sum <= mout[0] + mout[1] + mout[2] + mout[3] + mout[4] + mout[5] + mout[6] + mout[7];
yout_t <= sum;
end
end
`endif
assign yout = yout_t;
assign valid = valid_mult_r[0];
endmodule
---
**testbench**
The testbench is written as follows, with the main function being the continuous input of mixed signal data of 250KHz and 7.5MHz sine waves. The input mixed signal data can also be generated by MATLAB, see appendix for details.
## Example
`timescale 1ps/1ps
module test; //input reg clk; reg rst_n; reg en; reg [11:0] xin; //output wire valid; wire [28:0] yout;
parameter SIMU_CYCLE = 64'd2000; //50MHz sampling frequency
parameter SIN_DATA_NUM = 200; //simulation period
//===================================== // 50MHz clk generation localparam TCLK_HALF = 10_000; initial begin clk = 1'b0; forever begin # TCLK_HALF; clk = ~clk; end end
//============================ // reset and finish initial begin rst_n = 1'b0; # 30 rst_n = 1'b1; # (TCLK_HALF * 2 * SIMU_CYCLE); $finish; end
//======================================= // read signal data into register reg [11:0] stimulus [0: SIN_DATA_NUM-1]; integer i; initial begin $readmemh("../tb/cosx0p25m7p5m12bit.txt", stimulus); i = 0; en = 0; xin = 0; # 200; forever begin @(negedge clk) begin en = 1'b1; xin = stimulus[i]; if (i == SIN_DATA_NUM-1) begin //periodic data entry control i = 0; end else begin i = i + 1; end end end end
fir_guide u_fir_paral(
.xin(xin),
.clk(clk),
.en(en),
.rstn(rst_n),
.valid(valid),
.yout(yout)
);
endmodule ```
Simulation Results
From the simulation results below, it can be seen that after the FIR filter, the signal only has one low-frequency signal (250KHz), and the high-frequency signal (7.5MHz) is filtered out. Moreover, the output waveform is continuous and can be output continuously.
However, as shown in the red circle, the waveform starts with an irregular state.
When the starting end of the waveform is enlarged as shown in the figure below, it can be seen that the time interval of the irregular waveform, that is, the time interval between the two vertical lines, is 16 clock cycles.
Since the data is serially input, 16 sets of delay registers are used in the design, so the first normal point after filtering should be delayed by 16 clock cycles from the time when the first filtered data is output. That is, the valid signal of the data output should be delayed by another 16 clock cycles, which will make the output waveform more perfect.
Appendix: MATLAB Usage
Generate FIR Filter Coefficients
Open MATLAB and enter the command: fdatool in the command window.
Then the following window will open, set according to the FIR filter parameters.
Here, the FIR implementation method chosen is the least squares method (Least-squares), different implementation methods will have different filtering effects.
Click File -> Export
Export the filter parameters and store them in the variable coef, as shown in the figure below.
At this time, the coef variable should be floating-point data. Multiply it by a certain multiple to expand, and then take the approximate fixed-point data as the FIR filter parameter in the design. Here, the expansion multiple is taken as 2048, and the result is as follows.
Generate Input Mixed Signal
The signal is unsigned fixed-point data, with a bit width of 12 bits, stored in the file cosx0p25m7p5m12bit.txt.
Example
7.2 Verilog Parallel FIR Filter Design