6.2 Verilog System-Level Low-Power Design
Category Verilog Tutorial Advanced
Before writing code, establishing a comprehensive low-power plan at the system and architectural level can save more than 50% of the power consumption. Such low-power designs have little to do with code description and are usually designed by system and architectural personnel. These personnel need to have a wealth of hardware experience and be able to have a good overall grasp of the system. After the plan is formulated, it is handed over to functional design personnel (such as IC front-end designers, FPGA engineers, etc.) for implementation.
Multi-Voltage Technology
Generally speaking, the lower the voltage, the lower the power consumption, but the performance tends to be worse. Considering both power consumption and performance, different voltage designs can be adopted for different modules.
There are three main types of multi-voltage technology:
- Each voltage area has a fixed voltage, as shown in Figure 1.
- Each voltage area has a fixed voltage, and the selection of voltage is controlled by software, as shown in Figure 2.
- Adaptive method, the voltage of each area is variable, and the selection of voltage is also controlled by software, also known as dynamic voltage condition, as shown in Figure 3.
Generally speaking, the higher the supply voltage, the smaller the circuit delay, and the higher the performance. For example, the processor core and memory of a chip generally require higher performance, so a higher voltage scheme can be adopted. Other external designs can adopt a lower voltage scheme to reduce power consumption.
System Clock Distribution
Generally speaking, the higher the frequency, the better the performance, but the greater the power consumption. Reasonable clock distribution can also effectively reduce power consumption, and there are generally the following methods:
1. By clock division, each module adopts a reasonable working clock
Generally, the CPU bus requires a higher clock to meet higher design requirements, while the working frequency of peripherals such as UART and SPI is not very high. If the design treats everyone equally with a higher working frequency, it will obviously increase unnecessary power consumption.
Divide the high-speed clock to a certain extent and assign different modules. Under the condition of meeting the working performance, using a lower working clock frequency can effectively reduce power consumption.
2. Add multiple low-power working modes
Add multiple low-power clock distribution schemes in the design, and artificially select a working mode to reduce power consumption. Various low-power mode designs can refer to the following:
Mode | Description |
---|---|
Normal | The main clock uses a high-frequency PLL clock, which is fed into the design circuit |
Slow | The main clock uses a lower local clock |
Low-Power | The bus clock is turned off, only retaining the working clock of some peripherals |
Sleep | All clocks are turned off, and the entire design enters a sleep state |
3. Adaptive selection of working frequency
Similar to the voltage adaptive adjustment of multi-voltage technology, selecting the appropriate working frequency according to the current working state can also reduce power consumption.
For example, when a computer is processing some simple documents, a relatively lower working frequency can be selected; when a computer is processing some video rendering work, a relatively higher working frequency is needed.
The dynamic adjustment of working frequency and voltage is often a strategy that needs to be adopted simultaneously in low-power design.
Software and Hardware Division
The power consumption in the system is consumed by hardware units. In the design process, the functions of the system can be realized by hardware or software.
System designers predict (simulation modeling) the system performance according to design specifications and their own experience, deciding which part to implement with hardware and which part with software, in order to achieve the best balance between performance and power consumption. For example, some parameter calculations, after being calculated by software, are directly input to hardware, which is a more reasonable design.
In short, the division of software and hardware can greatly reduce power consumption, which is something that system designers need to consider carefully.
IP or Cell Library Selection
Nowadays, many designs also rely on the integration of IP. When selecting IP, under the condition of meeting the working performance, it is also necessary to reasonably select IP with relatively lower power consumption.
The standard cell library used in the design, although the same logical function is realized, will also have different voltage thresholds due to different process libraries.
LVT (Low Voltage Threshold), the threshold voltage is low, the saturation current is small, so such cell libraries have higher speed and greater leakage current.
HVT (High Voltage Threshold) cell leakage current is small, but the speed is slower.
SVT/RVT (Standard/Regular Voltage Threshold) performance is between LVT and HVT.
So when choosing the standard cell library, it is necessary to consider both speed and