5.3 Verilog Clock Division

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Keywords: Even Division, Odd Division, Fractional Division, Decimal Division

When starting with Verilog, many modules are composed of counters and dividers, such as PWM pulse width modulation, frequency meters, etc. Division logic is often completed through counting logic. This section mainly provides a simple summary of even division, odd division, fractional division, and decimal division.

Even Division

By using the method of connecting the reverse output end of the flip-flop to the input end, a simple 2 division circuit can be constructed.

Based on this, cascading can form 4 division, 8 division circuits.

The circuit implementation is shown in the figure below. When describing in Verilog, only simple inversion logic is needed.

If the even division coefficient is too large, it is necessary to cycle count the division coefficient N for division. When the counting period reaches the middle value of the division coefficient N/2, the clock is flipped to ensure that the duty cycle of the divided clock is 50%. Because it is an even division, you can also cycle count the middle value N/2 of the division coefficient.

An example of Verilog description for even division is as follows.

Example

module even_divisor
  # (parameter DIV_CLK = 10 )
    (
    input               rstn ,
    input               clk,
    output               clk_div2,
    output               clk_div4,
    output               clk_div10
    );

   //2 Division
   reg                   clk_div2_r ;
   always @(posedge clk or negedge rstn) begin
      if (!rstn) begin
         clk_div2_r     <= 'b0 ;
      end
      else begin
         clk_div2_r     <= ~clk_div2_r ;
      end
   end
   assign       clk_div2 = clk_div2_r ;

   //4 Division
   reg                   clk_div4_r ;
   always @(posedge clk_div2 or negedge rstn) begin
      if (!rstn) begin
         clk_div4_r     <= 'b0 ;
      end
      else begin
         clk_div4_r     <= ~clk_div4_r ;
      end
   end
   assign clk_div4      = clk_div4_r ;

   //N/2 Counting
   reg [3:0]            cnt ;
   always @(posedge clk or negedge rstn) begin
      if (!rstn) begin
         cnt    <= 'b0 ;
      end
      else if (cnt == (DIV_CLK/2)-1) begin
         cnt    <= 'b0 ;
      end
      else begin
         cnt    <= cnt + 1'b1 ;
      end
   end

   //Output Clock
   reg                   clk_div10_r ;
   always @(posedge clk or negedge rstn) begin
      if (!rstn) begin
         clk_div10_r <= 1'b0 ;
      end
      else if (cnt == (DIV_CLK/2)-1 ) begin
         clk_div10_r <= ~clk_div10_r ;
      end
   end
   assign clk_div10 = clk_div10_r ;
endmodule

The testbench only needs to provide the excitation clock and other signals, which are not listed here.

The simulation results are as follows.

Odd Division

Odd division, if the duty cycle is not required to be 50%, can be divided according to the method of even division. That is, the counter cycles the division coefficient N, and then selects a certain duty cycle to output the divided clock based on the count value.

If the high and low levels of the odd division output clock only differ by one cycle, the duty cycle of the divided clock can be adjusted to 50% by using the double-edged characteristics of the source clock and using "OR operation" or "AND operation".

OR operation to adjust the duty cycle

The timing diagram for generating a 3 division with a 50% duty cycle using the "OR operation" is as follows.

Using the rising edge of the source clock to divide a high level of 1 cycle and a low level of 2 cycles for a 3 division clock.

Using the falling edge of the source clock to divide a high level of 1 cycle and a low level of 2 cycles for a 3 By utilizing the dual-edge logic of a clock, it is possible to perform fractional division of the clock frequency. However, no matter how it is adjusted, the duty cycle of the fractional division cannot be 50%. There are many methods for fractional division, and here only one method similar to the adjustment of duty cycle in odd-numbered division is introduced.

(1) For example, when performing a 3.5 times division, the counter counts in a cycle up to 7, generating two divided clocks composed of 4 and 3 source clock cycles respectively. From the perspective of generating 2 divided clocks from 7 source clocks, this process completes a 3.5 times division, but each divided clock is not strictly divided by 3.5 times.
(2) The following adjusts the divided clock with uneven periods. In a single cycle count, two divided clocks composed of 4 and 3 source clock cycles are generated at the falling edge of the source clock respectively. Compared with the first time 2 uneven period clocks were generated, the phase of the 2 clocks generated this time is delayed by half a source clock cycle and advanced by half a source clock cycle respectively.
(3) By performing an "OR operation" on the clocks generated twice, a uniformly periodic 3.5 times divided clock can be obtained. The divided wave form diagram is shown below.

The Verilog description of 3.5 times clock division is as follows.

Example

module half_divisor(
    input               rstn ,
    input               clk,
    output               clk_div3p5
    );

   //Counter
   parameter            MUL2_DIV_CLK = 7 ;
   reg [3:0]            cnt ;
   always @(posedge clk or negedge rstn) begin
      if (!rstn) begin
         cnt    <= 'b0 ;
      end
      else if (cnt == MUL2_DIV_CLK-1) begin //Count 2 times the division ratio
         cnt    <= 'b0 ;
      end
      else begin
         cnt    <= cnt + 1'b1 ;
      end
   end

   reg                  clk_ave_r ;
   always @(posedge clk or negedge rstn) begin
      if (!rstn) begin
         clk_ave_r <= 1'b0 ;
      end
      //First cycle: 4 source clock cycles
      else if (cnt == 0) begin
         clk_ave_r <= 1 ;
      end
      //Second cycle: 3 source clock cycles
      else if (cnt == (MUL2_DIV_CLK/2)+1) begin
         clk_ave_r <= 1 ;
      end
      else begin
         clk_ave_r <= 0 ;
      end
   end

   //Adjust
   reg                  clk_adjust_r ;
   always @(negedge clk or negedge rstn) begin
      if (!rstn) begin
         clk_adjust_r <= 1'b0 ;
      end
      //This clock is only for adjusting the consistent duty cycle
      else if (cnt == 1) begin
         clk_adjust_r <= 1 ;
      end
      //This clock is only for adjusting the consistent exact division ratio
      else if (cnt == (MUL2_DIV_CLK/2)+1 ) begin
         clk_adjust_r <= 1 ;
      end
      else begin
         clk_adjust_r <= 0 ;
      end
   end

   assign clk_div3p5 = clk_adjust_r | clk_ave_r ;

endmodule

The simulation results are as follows.

Fractional Division

Basic Principle

Irregular fractional division cannot achieve that each clock cycle after division is a multiple of the source clock cycle, nor can it achieve that the duty cycle of the divided clock is all 50%, because Verilog cannot count the clock in decimal. Similar to the concept of "average frequency" introduced in the first division of half-integer division, fractional division is also implemented based on the method of variable division and multiple averaging.

For example, to perform a 7.6 times division, it is only necessary to ensure that the time of 76 source clock cycles is equal to the time of 10 divided clock cycles. At this time, it is necessary to perform 6 times 8 division and 4 times 7 division within 76 source clock cycles. For example, to perform a 5.76 division, it is necessary to perform 7 endmodule

The simulation results are as follows.

Clock Division Summary

Even division can achieve a 50% duty cycle clock division without using clock edge-triggered logic, which is the most ideal condition for division.

Odd division, if it is necessary to generate a 50% duty cycle division clock, requires the use of clock edge-triggered logic. If the duty cycle is not required, the implementation method is similar to that of even division.

Fractional division is a special type of fractional division, which can be designed using edge-triggered logic. When integrating two edge-triggered clock signals into the final output clock through certain logic, it is recommended not to use selection logic. This is because glitches are likely to occur, adding some uncertainty to the circuit. For example, the following description is not recommended.

assign clk_div3p5 = (cnt == 1 || cnt ==2) ? clk_ave_r 
                                          : clk_adjust_r ;

The basic idea of fractional division is that the average frequency of the output clock over a period of time meets the division requirements. However, considering phase jitter, it is also necessary to perform averaging operations on the division logic with variable division factors.