2.4 Verilog Expressions
Classification Verilog Tutorial
Expressions
Expressions are composed of operators and operands, and their purpose is to obtain a calculated result according to the meaning of the operator. Expressions can be used anywhere numerical values appear. For example:
Examples
a^b ; //XOR operation between a and b
address[9:0] + 10'b1 ; //Address increment
flag1 && flag2 ; //Logical AND operation
Operands
Operands can be of any data type, but some specific syntactic structures require the use of specific types of operands.
Operands can be constants, integers, real numbers, wires, registers, time, bit selections, field selections, memory, and function calls, etc.
Examples
module test;
//Real numbers
real a, b, c;
c = a + b ;
//Registers
reg [3:0] cprmu_1, cprmu_2;
always @(posedge clk) begin
cprmu_2 = cprmu_1 ^ cprmu_2;
end
//Function
reg flag1;
flag = calculate_result(A, B);
//Illegal operand
reg [3:0] res;
wire [3:0] temp;
always @(*) begin
res = cprmu_2 – cprmu_1;
//temp = cprmu_2 – cprmu_1; //Illegal, the assignment target in an always block cannot be of wire type
end
endmodule
Operators
Verilog provides about 9 types of operators, which are arithmetic, relational, equivalence, logical, bitwise, reduction, shift, concatenation, and conditional operators.
Most operators are similar to those in the C language. Among operators of the same type, except for the conditional operator which associates from right to left, the rest associate from left to right. Expressions within parentheses are executed first. For example, the two methods in each of the following groups are equivalent.
//Right to left association, both methods are equivalent
A+B-C;
(A+B)-C;
//Right to left association, both methods are equivalent, the result is B, D, or F
A ? B : C ? D : F;
A ? B : (C ? D : F);
//Right to left association, the two methods are not equivalent
(A ? B : C) ? D : F; //Result is D or F
A ? B : C ? D : F; //Result is B, D, or F
Between different operators, the precedence is different. The following table lists the order of operator precedence from high to low. When there are no parentheses, Verilog calculates the expression based on the operator precedence. To avoid confusion caused by operator precedence, it is recommended to use parentheses to distinguish expressions when the precedence is uncertain.
| Operator | Symbol | Precedence | ||
|---|---|---|---|---|
| Unary | + - ! ~ | Highest | ||
| Multiplication, Division, Modulo | * / % | |||
| Addition, Subtraction | + - | |||
| Shift | << >> | |||
| Relational | < <= > >= | |||
| Equivalence | == != === !== | |||
| Reduction | & ~& | |||
| XOR | ^ ~^ | |||
| OR | ~ | |||
| Logical | && | |||
| Conditional | ?: | Lowest |
Arithmetic Operators
Arithmetic operators include unary and binary operators.
Binary operators perform arithmetic operations on two operands, including multiplication (), division (/), addition (+), subtraction (-), exponentiation (*), and modulo (%).
Examples
reg [3:0] a, b;
reg [4:0] c;
a = 4'b0010;
b = 4'b1001;
c = a+b; //The result is c=b'b1011
c = a/b; //The result is c=4, truncated
If any bit of the operand is X, the calculation result will also be all Xs. For example:
Examples
b = 4'b100x;
c = a+b; //The result is c=4'bxxxx
When declaring variables, declare the bit width of the variables according to the operators to avoid overflow of the results. In the above example, the two variables being added have a bit width of 4 bits, so the result register variable should have a minimum bit width of 5 bits. Otherwise, During calculation, if the condition_expression is true (logical value of 1), the result of the operation is the true_expression; if the condition_expression is false (logical value of 0), the result of the calculation is the false_expression.
assign hsel = (addr[9:8] == 2'b0) ? hsel_p1 : hsel_p2;
//When the high 2 bits of the signal addr are 0, hsel is assigned the value of hsel_p1; otherwise, hsel_p2 is assigned to hsel.
In fact, the conditional expression is similar to a 2-way (or multi-way) selector, and its description can be completely replaced with if-else statements.
Of course, the conditional operator can also be nested to perform multi-level selection logic. For example:
Example
assign hsel = (addr[9:8] == 2'b00) ? hsel_p1 :
(addr[9:8] == 2'b01) ? hsel_p2 :
(addr[9:8] == 2'b10) ? hsel_p3 :
(addr[9:8] == 2'b11) ? hsel_p4;
-1.3 Setting Up the Verilog Environment
-2.2 Numerical Representation in Verilog
- 2.4 Verilog Expressions
-2.5 Verilog Compilation Instructions
-3.1 Continuous Assignment in Verilog
-4.1 Process Structures in Verilog
-4.2 Process Assignment in Verilog
-4.3 Timing Control in Verilog
-4.4 Statement Blocks in Verilog
-4.5 Conditional Statements in Verilog
-4.6 Multi-way Branch Statements in Verilog
-4.7 Loop Statements in Verilog
-4.8 Continuous Process Assignment in Verilog
-5.1 Modules and Ports in Verilog
-5.2 Instantiation of Modules in Verilog
-5.3 Parameterized Instantiation in Verilog
-6.3 State Machines in Verilog
-6.4 Competition and Hazards in Verilog
-6.5 Avoiding Latches in Verilog
-6.7 Pipeline Design in Verilog
-7.1 Design of Dividers in Verilog
-7.2 Design of Parallel FIR Filters in Verilog
-7.3 Design of Serial FIR Filters in Verilog
-7.4 Design of CIC Filters in Verilog
-8.1 Numerical Conversion in Verilog