4.4 Verilog Statement Blocks
Category Verilog Tutorial
Keywords: Sequential block, Parallel block, Nested block, Named block, disable
Verilog statement blocks provide a mechanism for combining two or more statements into a syntax structure that is equivalent to a single statement. There are mainly two types: sequential blocks and parallel blocks.
Sequential Block
Sequential blocks are denoted by the keywords begin and end.
Statements within a sequential block are executed one by one. Of course, non-blocking assignments are an exception.
The timing of each statement in a sequential block is always related to the time when the preceding statement is executed.
In simulations before this section, blocking assignments in the initial block are instances of sequential blocks.
Parallel Block
Parallel blocks are represented by the keywords fork and join.
Statements within a parallel block are executed concurrently, even if they are in a blocking form.
The timing of each statement in a parallel block is related to the time when the block statement begins to execute.
The difference between sequential and parallel blocks is obvious, and the following simulation illustrates this.
Simulation code is as follows:
Example
`timescale 1ns/1ns
module test ;
reg [3:0] ai_sequen, bi_sequen ;
reg [3:0] ai_paral, bi_paral ;
reg [3:0] ai_nonblk, bi_nonblk ;
//============================================================//
//(1)Sequence block
initial begin
#5 ai_sequen = 4'd5 ; //at 5ns
#5 bi_sequen = 4'd8 ; //at 10ns
end
//(2)fork block
initial fork
#5 ai_paral = 4'd5 ; //at 5ns
#5 bi_paral = 4'd8 ; //at 5ns
join
//(3)non-block block
initial fork
#5 ai_nonblk <= 4'd5 ; //at 5ns
#5 bi_nonblk <= 4'd8 ; //at 5ns
join
endmodule
Simulation results are as follows:
For parallel blocks, the assignments of ai_paral and bi_paral are executed simultaneously, so both are assigned at 5ns.
Non-blocking assignments can also achieve the same effect as parallel blocks.
Nested Block
Sequential and parallel blocks can also be used in a nested manner.
Simulation code is as follows:
Example
`timescale 1ns/1ns
module test ;
reg [3:0] ai_sequen2, bi_sequen2 ;
reg [3:0] ai_paral2, bi_paral2 ;
initial begin
ai_sequen2 = 4'd5 ; //at 0ns
fork
#10 ai_paral2 = 4'd5 ; //at 10ns
#15 bi_paral2 = 4'd8 ; //at 15ns
join
#20 bi_sequen2 = 4'd8 ; //at 35ns
end
endmodule
Simulation results are as follows:
Statements within a parallel block are executed in parallel, so signals ai_paral2 and bi_paral2 are assigned at 10ns and 15ns respectively. The longest execution time within the parallel block is 15ns, so the signal bi_sequen2 in the sequential block is assigned at 35ns.
Named Block
We can name the block statement structure.
Local variables can be declared in a named block, and variables can be accessed through hierarchical naming.
Simulation code is as follows:
Example
``
timescale 1ns/1ns
module test;
initial begin: tutorialpro //Named block name is tutorialpro, semicolon is required
integer i ; //This variable can be used by other modules through test.tutorialpro.i
i = 0 ;
forever begin
#10 i = i + 10 ;
end
end
reg stop_flag ;
initial stop_flag = 1'b0 ;
always begin : detect_stop