2.5 Verilog Compilation Directives
Category Verilog Tutorial
Identifiers that begin with backticks ``` are Verilog system compilation directives.
Compilation directives provide great convenience for writing, compiling, and debugging Verilog code.
The following introduces the complete 8 compilation directives, of which the first 4 are more frequently used.
define,undef
During the compilation phase, `define is used for text substitution, similar to #define in C language.
Once the `define directive is compiled, it will be effective throughout the compilation process. For example, define in one file:
`define DATA_DW 32
Then in another file, DATA_DW can also be used directly.
`define S $stop;
// Use `S to replace the system function $stop; (including the semicolon)
`define WORD_DEF reg [31:0]
// `WORD_DEF can be used to declare a 32-bit register variable
`undef is used to cancel the previous macro definition, for example:
`define DATA_DW 32
...
reg [DATA_DW-1:0] data_in;
...
`undef DATA_DW
ifdef,ifndef, elsif,else, `endif
These are conditional compilation directives. For example, in the following example, if MCU51 is defined, the first parameter description is used; if neither MCU nor WINDOW is defined, the second parameter description is used; if neither is defined, the third parameter description is used.
`ifdef MCU51
parameter DATA_DW = 8;
`elsif WINDOW
parameter DATA_DW = 64;
`else
parameter DATA_DW = 32;
`endif
The elsif andelse compilation directives are optional for the ifdef directive, that is, there can be onlyifdef and `endif to form a conditional compilation directive block.
Of course, `ifndef can also be used for conditional compilation, indicating that if there is no relevant macro definition, the relevant statements are executed.
In the following example, if WINDOW is defined, the second parameter description is used. If WINDOW is not defined, the first parameter description is used.
Example
`ifndef WINDOW
parameter DATA_DW = 32;
`else
parameter DATA_DW = 64;
`endif
`include
Using `include, a Verilog file can be embedded into another Verilog file during compilation, similar to the #include structure in C language. This directive is usually used to include global or common header files in the design file.
The file path can use either a relative path or an absolute path.
`include "../../param.v"
`include "header.v"
`timescale
In Verilog models, time delays have specific unit time expressions and are associated with actual time using the `timescale compilation directive.
This directive is used to define the units and precision of time delays and simulation, with the format:
`timescale time_unit / time_precision
time_unit represents the unit of time, and time_precision represents the precision of time, both of which are composed of numbers and units s (seconds), ms (milliseconds), us (microseconds), ns (nanoseconds), ps (picoseconds), and fs (femtoseconds). The time precision can be the same as the time unit, but the size of the time precision cannot exceed the size of the time unit. For example, in the following example, the output end Z will output the result of A&B after a delay of 5.21ns.
Example
`timescale 1ns/100ps // Time unit is 1ns, precision is 100ps, legal
// `timescale 100ps/1ns // Not legal
module AndFunc(Z, A, B);
output Z;
input A, B;
assign #5.207 Z = A & B;
endmodule
During compilation, the timescale directive affects the time delay values in all subsequent modules until anothertimescale directive or `resetall directive is encountered.
Since there is no default timescale in Verilog, iftimescale is not specified, Verilog modules will inherit the `timescale parameter of the previously compiled module, which may lead to design errors.
If multiple modules in a design have `timescale, the simulator always sets the minimum time delay precision of all modules, and all time delays are correspondingly converted to the minimum time delay precision, while the time delay unit is not affected. For example:
Example
``
timescale 10ns/1ns
module test;
reg A, B;
wire OUTZ;