1.1 Types of Verilog Gates
Classification Advanced Verilog Tutorial
Keywords: Tri-state gate, Pull-up/pull-down, Selector
Gate-level modeling involves the use of basic logical units such as AND gates, NAND gates, etc., for design at a lower level of abstraction. Compared to behavioral modeling, gate-level modeling focuses more on the implementation of hardware, that is, achieving various logical functions by connecting basic gate circuits. Although behavioral modeling is eventually synthesized into a basic gate circuit network, the efficiency of behavioral modeling is far higher than that of gate-level modeling for complex designs. Therefore, Verilog is mostly used to describe the behavioral level of digital design (RTL), generally focusing only on the algorithm or process of design implementation, without particular concern for the specific hardware implementation method.
Some designs, such as gated clocks, require the use of basic gate units to increase the controllability and reliability of the circuit.
Multi-Input Gates
Multi-input gates have only a single output, with one or more input terminals. The built-in multi-input gates in Verilog are as follows:
and (AND gate), nand (NAND gate), or (OR gate), nor (NOR gate), xor (XOR gate), xnor (XNOR gate)
When implementing simple logical functions using basic logical gate units, the method of module instantiation can be used.
The first port of the gate-level unit is the output, and the subsequent ports are inputs. Attention should be paid to the order when calling the instantiation.
When instantiating the gate-level unit, you can also omit the name of the instance, which facilitates code writing.
When the number of input ports exceeds 2, simply continue to arrange the input signals in the port list, and Verilog can automatically recognize them.
Example
//basic gate instantiation
and a1 (OUTX, IN1, IN2);
nand na1 (OUTX1, IN1, IN2);
or or1 (OUTY, IN1, IN2);
nor nor1 (OUTY1, IN1, IN2);
//3 input
xor xor1 (OUTZ, IN1, IN2, IN3);
//no instantiation name
xnor (OUTZ1, IN1, IN2);
The truth table for multi-input gates is as follows, note that the output will not appear as Z
.
Multi-Output Gates
Multi-output gates have only a single input, with one or more output terminals, and can also be referred to as buffers, serving the role of buffering and delaying.
The built-in multi-output gates are as follows:
buf (buffer)
not (NOT gate)
Similar to multi-input gates, multi-output gates can be called using the method of module instantiation.
The first port of the gate-level unit is the output, and the last port is the input. When the number of output ports exceeds 1, the output signals need to be arranged before the last input port.
The name of the instance can also be omitted during instantiation.
Example
//buf
buf buf1 (OUTX2, IN1);
//2 output
buf buf2 (OUTY2, OUTY3, IN2);
//no instantiation name
not (OUTZ3, IN3);
The truth table for multi-output gates is as follows, note that the output will not appear as Z
.
buf | 0 | 1 | x | z | not | 0 | 1 | x | z | |
---|---|---|---|---|---|---|---|---|---|---|
Output | 0 | 1 | x | x | Output | 1 | 0 | x | x |
Tri-state Gates
Verilog also provides 4 buffer gate units with a control terminal, called tri-state gates. Data can only be transmitted normally when the control signal is valid; otherwise, the output is in a high-impedance state Z
.
The names and symbols of the 4 tri-state gates are as follows:
When instantiating, the first port of the tri-state gate is the output, the second port is the data input, and the third port is the control input. The order of signal arrangement should be consistent when instantiating.
Tri-state gates do not support more than 1 output port, but the name of the instance can be omitted during instantiation.
Example
``` //tri bufif1 buf1 (OUTX, IN1, CTRL1); bufif0 buf2 (OUTY, IN1, CTRL2); notif1 buf3 (OUTZ, IN1, CTRL3); //no instantiation name notif0 (OUTX1, IN1, CTRL4