5.1 Verilog Modules and Ports
Category Verilog Tutorial
Keywords: Module, Port, Bidirectional Port, PAD
There are three types of structural modeling description statements: Gate (gate-level) instantiation statements, UDP (User Defined Primitive) instantiation statements, and module (module) instantiation statements. This time, we mainly talk about the most commonly used module-level instantiation statements.
Module
A module is the definition form of the basic unit in Verilog and is the interface for interaction with the outside world.
The module format is defined as follows:
module module_name
#(parameter_list)
(port_list) ;
Declarations_and_Statements ;
endmodule
The module definition must start with the keyword module and end with the keyword endmodule.
The module name, port signals, port declarations, and optional parameter declarations appear before the Verilog statements used in the design (Declarations_and_Statements in the figure).
Inside the module, there are five optional parts, which are variable declarations, data flow statements, behavioral statements, low-level module instantiations, and tasks and functions, as shown in the figure. The order and position of these five parts are arbitrary. However, all kinds of variables should be declared before use. The specific position of the variable declaration is not required, but it must be in a position before use.
Most of the simulation codes before will use the module declaration, which you can refer to by yourself, and I will not give specific examples here. The following introduction to the port will be more detailed simulation.
Port
The port is the interface for the module to interact with the outside world. For the external environment, the inside of the module is invisible, and the call to the module can only be carried out through the port connection.
Port List
The module definition contains an optional port list, which generally lists signal variables without type and bit width in the module declaration. The following is a port list of a PAD model:
module pad(
DIN, OEN, PULL,
DOUT, PAD);
A module that does not interact with the external environment can be declared without a port list. For example, the test module in the test.sv file we simulated before did not declare specific ports.
module test ; //Direct semicolon end
...... //Data flow or behavioral description
endmodule
Port Declaration
(1) After the port signals are listed in the port list, they can be declared in the module entity.
According to the direction of the port, there are three types of port: input, output, and inout.
The input and inout types cannot be declared as reg data types because the reg type is used to store values, while the input port can only reflect the changes of the external signals connected to it and cannot store the values of these signals.
The output can be declared as either wire or reg data types.
The port declaration in the above example of the pad module can be represented in the module entity as follows:
Example
//Port type declaration
input DIN, OEN ;
input [1:0] PULL ; //(00,01-dispull, 11-pullup, 10-pulldown)
inout PAD ; //pad value
output DOUT ; //pad load when pad configured as input
//Port data type declaration
wire DIN, OEN ;
wire [1:0] PULL ;
wire PAD ;
reg DOUT ;
(2) In Verilog, the port is implicitly declared as a wire variable, that is, when the port has a wire attribute, it is not necessary to declare the port type as wire again. However, when the port has a reg attribute, the reg declaration cannot be omitted.
The port declaration in the above example can be simplified as follows:
Example
//Port type declaration
input DIN, OEN ;
input [1:0] PULL ;
inout PAD ;
output DOUT ;
reg DOUT ;
(3) Of course, the declaration of the signal DOUT can be completely combined into one sentence:
output reg DOUT ;
(4) There is also a more concise and commonly used method to declare ports, which is to list the ports and their types when declaring the module. The reg type port can be declared either when declaring the module or in the module entity, for example, the following two methods are equivalent.
Example
``` module pad( input DIN, OEN , input [1:0] PULL , inout PAD , output reg DOUT ); module pad(
5.1 Verilog Modules and Ports