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1.2 Verilog Switch-Level Modeling

Category Verilog Tutorial Advanced

Keywords: MOS, CMOS, Bidirectional Switch, PAD

Switch-level modeling is a design at a lower level of abstraction than gate-level modeling. In very rare cases, designers may choose to use transistors as the underlying modules of their designs. With the increasing complexity of circuit design and the emergence of advanced tools, digital design based on switches is gradually fading. At present, Verilog only provides digital design capabilities with logical values 0, 1, x, z as related driving strengths, so transistors in Verilog are also only regarded as switches that are either on or off.

MOS Switch

There are two types of MOS switches, declared with the following keywords:

nmos (N-type MOS tube) pmos (P-type MOS tube)
rnmos (NMOS tube with high impedance) rpmos (PMOS tube with high impedance)

MOS tubes are used to model switch logic, with data flowing from input to output, and the data flow can be turned on or off by appropriate settings.

MOS tubes with impedance have a higher impedance from the source to the drain, and they reduce the strength of the signal when transmitting signals.

The structure diagram of the MOS tube switch is shown below.

When instantiating, the first port of the MOS tube is the output end, the second port is the data input end, and the third port is the control input end.

Example

//tri
pmos pmos1 (OUTX, IN1, CTRL1);
//no instantiation name
nmos (OUTX1, IN1, CTRL2);

The truth table of the MOS tube is shown below, which is very similar to the tri-state gate.

nmos Control pmos Control
0 1 x z 0 1 x z
0 z 0 0/z 0/z 0 0 z 0/z 0/z
1 z 1 1/z 1/z 1 1 z 1/z 1/z
x z x x x x x z x x
z z x x x z x z x x

CMOS Switch

CMOS switches are declared with the keywords cmos and rcmos (with high impedance).

CMOS has one data output, one data input, and two control inputs. The structural diagram is as follows:

The signals PControl and Ncontrol are usually complementary. When the signal Ncontrol is 1 and PControl is 0, the switch is on. When the signal Ncontrol is 0 and PControl is 1, the switch outputs a high impedance. The CMOS switch can be regarded as a combination of NMOS and PMOS switches.

When instantiating, the first port of the CMOS tube is the output end, the second port is the data input end, the third port is the Ncontrol control input end, and the fourth port is the Pcontrol control input end.

The instantiation format of the CMOS switch is as follows.

Example

//coms
cmos c1 (OUTY, IN1, NCTRL, PCTRL);
//no instantiation name
cmos (OUTY1, IN1, NCTRL, PCTRL);

Since CMOS can be regarded as a combination of NMOS and PMOS switches, these two types of MOS switches can also be used to build CMOS switches, as follows:

Example

//the same 2-way instantiation of cmos
nmos n2 (OUTY, IN1, NCTRL);
pmos p2 (OUTY, IN1, PCTRL);

The truth table of CMOS is similar to that of MOS switches, paying attention to the complementarity of the Ncontrol and Pcontrol signals.

Bidirectional Switch

NMOS, PMOS, and CMOS switch gates all conduct from the drain to the source, and the direction is unidirectional. Verilog also provides bidirectional switch devices, where data can flow in both directions, and signals on both sides can be driving signals.

The keyword declarations for bidirectional switches and their impedance modes are as follows:

tran tranif1 tranif0 rtran rtranif1 rtranif0

The structure diagram test_io_conn(PULL_DOWN, IO2_OUT, IO3_IN); OEN[3] = 1'b0; OEN[2] = 1'b1; test_io_conn(PULL_DOWN, IO3_OUT, IO2_IN); end PADUP u_pad_up0(DIN[0], OEN[0], PAD[0], DOUT[0]); PADUP u_pad_up1(DIN[1], OEN[1], PAD[1], DOUT[1]); PADDOWN u_pad_down3(DIN[2], OEN[2], PAD[2], DOUT[2]); PADDOWN u_pad_down4(DIN[3], OEN[3], PAD[3], DOUT[3]); initial begin forever begin

100;

//$display("---gyc---%d", $time); if ($time >= 1000) begin $finish; end end end endmodule // test

The simulation results are as follows.

As shown in the figure, within 13ns, when all four PADs are inputs, the PAD values correspond to the pull functions, that is, PAD0-1 both have pull-up functions, and PAD2-3 both have pull-down functions.

Between 13-53ns, PAD0 is an output, PAD1 is an input, and they are connected, the logical value changes of the two are consistent. Similarly, between 53ns-93ns, PAD1 is an output, PAD0 is an input, and the logical values are also consistent when connected. This indicates that the input and output functions of PAD0/1 are normal.

The results for PAD2/3 are similar, and are not described here.

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