3.5 Verilog Delay Back-Annotation
Category Advanced Verilog Tutorial
Keywords: Delay Back-Annotation, SDF
Delay back-annotation is the process where designers, based on the unit library process, gate-level netlist, and capacitance and resistance information in the layout, use digital design tools to annotate delay information into the gate-level netlist. With the netlist after delay back-annotation, precise timing simulation can be performed, making the simulation closer to the actual working digital circuit.
Delay Back-Annotation Process
The simulations in the previous tutorials were basically functional simulations. Whether it is IC design or FPGA development, timing simulation is indispensable. The section "1.4 Verilog Design Methods" in the "Verilog Tutorial" also describes the complete digital design and development process.
Below, it is explained how delay back-annotation is used in this process, as a review and consolidation.
(1) Use hardware description language to complete the RTL level description and perform functional simulation.
(2) Apply certain timing constraints to signals such as clocks, resets, and output ports, including the setting of clock frequency, timing checks, delays, and other information, and use them for logic synthesis.
(3) The synthesized gate-level netlist contains various roughly estimated delay information. At this point, you can remove hold, recovery, removal, interconnect (interconnection line), and other delay information to perform preliminary timing simulation and static timing analysis (STA), and preliminarily verify whether the setup and other timing requirements are met. Many companies or individuals will also skip this step of simulation.
(4) Perform layout and routing of the gate-level netlist to convert it into a layout-level netlist. Based on the geometric shape of the components and the manufacturing process, capacitance and resistance information in the layout circuit can be extracted, and then the delay values in the layout can be calculated based on this information.
(5) Back-annotate the delay information in the layout after layout and routing into the layout-level netlist, which allows precise modification of the delay values in the netlist. At this time, perform timing simulation and STA again to verify whether the timing is met.
(6) If all verifications pass, you can proceed with download or implementation and production. If there is a timing violation, first check whether there are any issues with the timing constraint settings, such as delay parameters, clock frequency, signal relationships, etc., and then re-layout and route to verify whether the violation can be eliminated. If the above measures cannot eliminate the violation, it is necessary to return to the design initial and optimize the RTL description.
The following is a schematic diagram of this process, where the highlighted part represents the additional operation description that can be added in the digital design process.
SDF File
SDF (Standard Delay Format) is a standard delay format file commonly used for delay back-annotation. This file contains all the IOPATH, INTERCONNECT, TIMING CHECK, and other delay time and timing constraint parameters used for simulation. The following is a brief introduction to the SDF file.
File Format
The SDF file is declared with the keyword DELAYFILE and includes keywords such as DESIGN, DATE, and other information.
Delay time and timing constraint parameters are all described within CELL.
The SDF file is composed of file declaration information and many different CELLs, as follows.
(DELAYFILE
(DESIGN "top")
(DATE "Love Sep 7 11:11:11 2017")
......
(TIMESCALE 1ns)
(CELL
......
)
(CELL
......
)
......
)
Delay Types
The delay types in the SDF file include cell delay and wire delay. Cell delay refers to the delay inside the logic gate unit, and wire delay refers to the delay between devices connected by wire.
The cell delay description is as follows, defining the rising delay and falling delay of the input ports (A/B) and the output port (Z) in the module "and_gate", and specifying the minimum and maximum values.
(CELL
(CELLTYPE "and_gate") //module name
(INSTANCE u_and) //instance name, if multi-level access is required, specify the access level
(DELAY
(ABSOLUTE
(IOPATH A Z (1.5::1.8) (1.3::1.7)) //rising delay minimum value 1.5, maximum value 1.8
(IOPATH B Z (1.5::1.8) (1.3::1.7)) //falling delay minimum value 1.3, maximum value 1.7
)
)
)
Wire Keep the parameters involved in the example of the SDF file unchanged, integrate multiple CELL descriptions into a complete SDF file, and name it "simple_test.sdf".
Add the following statement to the testbench to back-annotate the delay information from the SDF file to the top module of the design and perform timing simulation again.
initial begin
$sdf_annotate("../rtl/simple_test.sdf", u_top, , "sdf.log", "MAXIMUM", ,);
end
The timing simulation and log print information are as follows, as can be seen from the diagram:
(1) The rise delay from the input ends A/B to the output end Z of the AND gate is 33.8-32=1.8ns;
(2) The interconnect delay from the output end Z of the AND gate to the input end D of the flip-flop is 34.551-33.8=0.751ns, no longer 0;
(3) The time difference from the D end to the CP end of the flip-flop is 35-34.551=0.449ns, which is less than the 1ns set for the setup check, so the timing does not meet the requirements, and information about the violation will be printed.
(4) The rise delay from the CP end to the output end Q of the flip-flop is 37.3-35=2.3ns;
In summary, the simulation results are consistent with the design parameters, but there is a timing violation. The main reason is that the data at the input end of the AND gate and the clock of the flip-flop are asynchronous and unrelated. To solve such asynchronous issues, please refer to the next chapter "Chapter 4: Synchronization and Asynchrony".
It should be noted:
Compared with the specify block statements, the SDF file can also specify inter-module wire delays.
Generally speaking, using an SDF file to specify the timing information of the layout-level netlist is the closest to the actual digital circuit, and compared with the RTL or the gate-level netlist synthesized, the timing of this version is the worst.
When the SDF file specifies the delay of the path within the module, the original module's specify block must be retained, and the conditions, types, etc., specified in the specify block and the SDF file must be consistent, while the delay values can be different. For example, specify the delay unconditionally in the specify block:
(A => Z) = (1.3, 1.7);
Specify conditional delay in the SDF file:
(COND A==1'b1&&B==1'b1 (IOPATH A Z (1.5::1.8) (1.3::1.7)))
Then an SDF Warning "IOPATH from A to Z is not found." will be reported during the compilation phase. The delay set by the SDF file is invalid. The SDF file should also specify the path delay unconditionally.
This time, the SDF file was manually written just to introduce the SDF file and its usage. In fact, SDF files are all generated by designers with the help of IC design tools (such as PrimeTime), and the previous note does not need to be too worried, just pay attention during debugging. Generally, the number of gate-level netlists in digital design is huge, and it is also impractical to write SDF files manually.
Download the source code for this chapter
-0.3 Verilog Code Specification
-1.2 Verilog Switch-Level Modeling
-2.1 Basic Knowledge of Verilog UDP
-2.2 Verilog Combinational Logic UDP
-2.3 Verilog Sequential Logic UDP
-3.2 Verilog specify Block Statements
-3.3 Verilog Setup and Hold Time
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