2.3 Verilog Sequential Logic UDP

Category Advanced Verilog Tutorial

Sequential Logic UDPs differ from combinational logic UDPs in both definition form and behavioral functionality, with the main differences as follows:

1. The output of a sequential logic UDP must be declared as of type reg.
1. Sequential logic UDPs can be initialized with an initial statement.

The state table format is slightly different:

...    :  <current_state>  :  <next_state>  ;

1. Each row of the sequential logic UDP state table consists of three parts: the input section, the current state, and the output state, separated by colons ":".
1. current_state is the current value of the output register, and next_state is the new value of the output register. next_state is determined by the input and current_state together.
1. The input items of the state table can be levels or edge transitions.

The representation of sequential logic UDPs is mainly divided into two types: level-triggered UDPs and edge-triggered UDPs.

Level-Triggered UDP

The output of a level-triggered UDP changes based on the change in the input level state.

The functional description of a D latch with a reset end is as follows:

When the reset end is 1, the output is always 0;
When the reset end is 0 and the enable control end is 1, the latch is transparent, and the output is equal to the input;
When the reset end is 0 and the enable control end is 0, the latch is in a hold state, and the output remains unchanged.

Its truth table is (q represents the current state, q+ represents the next state):

In fact, the process of writing a UDP can be understood as a process of writing a truth table in a different format.

The UDP of a D latch with a reset end can be described as follows:

primitive d_latch(q, clear, en, d);
    output q;
    reg q;
    input d, en, clear;

    initial
        q = 0;

    table
    //clear      en      d      :q      :q+;
    1           ?        ?       :?      :0;   //clear
    0           0        ?       :?      :-;    //"-" means stable

    0           1        0       :?      :0;   //q = d
    0           1        1       :?      :1;
    endtable
endprimitive

Of course, you can also declare the type and assign initial values when listing port signals.

primitive d_latch2(
    output reg q = 0,
    input clear, en, d);
    ...
endprimitive

Edge-Triggered UDP

The output of an edge-triggered UDP changes based on the input edge transitions and/or changes in the input level state.

Directly provide the "truth table" of a D flip-flop with an asynchronous reset end (RST) and captures the signal on the falling edge of the clock:

It can be seen that this "truth table" also adds the concept of rising and falling edges, which is convenient for writing UDP code.

The sequential logic UDP description of this D flip-flop is as follows:

primitive D_TRI(
    output reg Q = 0,
    input RST, CP, D);
table
//RST      CP      D      :Q      :Q+;
//(1) Reset
1           ?        ?       :?      :0;  //RST=1 resets to zero
(??)        ?        ?       :?      :-;  //Ignore RST edge changes
//(2) Capture on falling clock edge
0           (10)     0       :?      :0;  //Capture signal on falling clock edge
0           (10)     1       :?      :1;
//possible negedge
0           (1x)     ?       :?      :-;  //May hold on falling clock edge
0           (x0)     ?       :?      :-;
//(3) Hold on rising clock edge
0           (0?)     ?       :?      :-;  //Hold on rising clock edge
//possible posedge
0           (x1)     ?       :?      :-;  //May hold on rising clock edge
//(4) Even if there is a data transition when not on a clock edge, the output still holds
0           ?        (??)    :?      :-;
endtable
endprimitive // D_TRI

Perform a simple simulation on this

4.3 Verilog Cross-Clock Domain Transfer: Fast to Slow

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