3.2 Verilog specify block statements
Category Advanced Verilog Tutorial
Keywords: specify, path delay
Path delays are described with the keywords specify and endspecify, which form the specify block statement.
The specify block is an independent part of a module and should not appear within other statement blocks (initial, always, etc.).
The specify block statement mainly has the following functions:
Specify the pin-to-pin delays in all paths;
Define specparam constants;
Set up timing checks in the circuit.
Parallel Connection
Each path has a source pin and a destination pin, and describing the delays of these paths in sequence with specify statements is called parallel connection.
The usage format of parallel connection is as follows:
(<source_io> => <destination_io>) = <delay_value> ;
A model description of a 4-input AND logic module with path delays is as follows:
Example
module and4(
output out,
input a, b, c, d);
specify
(a => out) = 2.5 ;
(b => out) = 2.5 ;
(c => out) = 3.5 ;
(d => out) = 3.5 ;
endspecify
wire an1, an2 ;
and (an1, a, b);
and (an2, c, d);
and (out, an1, an2);
endmodule
The keyword specparam can be used to define delay value constants within the specify block, which can then be assigned to path delays.
Constants defined by specparam can only be used within the specify block.
Example
specify
specparam ab_2_out = 2.5 ;
specparam cd_2_out = 3.5 ;
(a => out) = ab_2_out ;
(b => out) = ab_2_out ;
(c => out) = cd_2_out ;
(d => out) = cd_2_out ;
endspecify
In parallel connections, the source pin and the destination pin correspond one-to-one. Parallel connections also support the description of path delays between multi-bit signals, but the bit width must be consistent.
Example
module paral_conn(
input [3:0] d,
output [3:0] q);
specify
(d => q) = 3 ;
endspecify
assign q = d & 4'b0101 ;
endmodule
Here, the specify block statement can also be expanded to describe, and both expressions are equivalent.
Example
specify
(d[0] => q[0]) = 3 ;
(d[1] => q[1]) = 3 ;
(d[2] => q[2]) = 3 ;
(d[3] => q[3]) = 3 ;
endspecify
Full Connection
In a full connection, each bit of the source pin is connected to each bit of the target pin.
The connection between the source pin and the destination pin is traversed in combination, and the bit width does not need to correspond.
The usage format of full connection is as follows:
(<multiple_source_io> *> <multiple_destination_io>) = <delay_value> ;
For example, a 4-input AND logic module can be described as follows:
Example
module and4(
output out,
input a, b, c, d);
specify
(a,b *> out) = 2.5 ;
(c,d *> out) = 3.5 ;
endspecify
wire an1, an2 ;
and (an1, a, b);
and (an2, c, d);
and (out, an1, an2);
endmodule
Edge-Sensitive Paths
Edge-sensitive paths are used for timing modeling of input-to-output delays and use edge identifiers to specify triggering conditions. If not specified, any change will trigger a change in the delay value from the source pin to the destination pin.
An example of usage is as follows:
Example
``` //On the rising edge of clk, the path delay from clk to out rising is 1, falling is 2
3.2 Verilog Specify Block Statements