3.2 Verilog Delay

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3.2 Verilog Delay

Category Verilog Tutorial

Keywords: Delay, Inertial Delay

The delay in continuous assignment statements is used to control the time delay between any operand change and the assignment of the new value to the left-hand side.

Delay is generally not synthesizable.

The delay of registers can also be controlled, which is explained in the timing control section.

Continuous assignment delay can generally be divided into regular assignment delay, implicit delay, and declared delay.

The following three examples achieve the same function, corresponding to three different ways of writing continuous assignment delays.

// Regular delay, the result of A&B is assigned to Z after a 10-time unit delay
wire Z, A, B;
assign #10 Z = A & B;

// Implicit delay, a wire variable is declared and continuously assigned with a certain delay.
wire A, B;
wire #10 Z = A & B;

// Declared delay, a wire variable is declared with a specified delay. Therefore, all continuous assignments to this variable will be postponed to the specified time. This method is generally not recommended unless for gate-level modeling.
wire A, B;
wire #10 Z;
assign Z = A & B;

Inertial Delay

In the above examples, if either A or B changes, there will be a 10-time unit delay before Z gets the new value. If within these 10 time units, i.e., before Z gets the new value, either A or B changes again, the new value of Z will be calculated based on the current new values of A or B. This is called inertial delay, meaning that signal pulses narrower than the delay will have no effect on the output.

Therefore, when simulating, the delay must be set reasonably to prevent certain signals from not being effectively delayed.

Delay simulation of an AND gate logic with delay.

Example

module time_delay_module(
    input ai, bi,
    output so_lose, so_get, so_normal);

    assign #20 so_lose = ai & bi;
    assign #5 so_get = ai & bi;
    assign so_normal = ai & bi;
endmodule

Testbench reference is as follows:

Example

`timescale 1ns/1ns

module test;
    reg ai, bi;
    wire so_lose, so_get, so_normal;

    initial begin
        ai = 0;
        #25; ai = 1;
        #35; ai = 0; //60ns
        #40; ai = 1; //100ns
        #10; ai = 0; //110ns
    end

    initial begin
        bi = 1;
        #70; bi = 0;
        #20; bi = 1;
    end

    time_delay_module u_wire_delay(
        .ai (ai),
        .bi (bi),
        .so_lose (so_lose),
        .so_get (so_get),
        .so_normal (so_normal));

    initial begin
        forever begin
            #100;
            //$display("---gyc---%d", $time);
            if ($time >= 1000) begin
                $finish;
            end
        end
    end

endmodule

Simulation results are as follows:

The signal so_normal is the normal AND logic.

Since all delays are greater than 5ns, the result of the signal so_get is the AND operation followed by a 5ns delay.

The first part of the signal so_lose is the result of the AND operation followed by a 20ns delay.

Since the second high pulse duration of signal ai is less than 20ns, the signal so_lose will miss the delayed detection of this pulse due to inertial delay, so the second half of the so_lose signal remains 0.