2.2 Verilog Combinational Logic UDP

❮ Python Openssl Vulnerability Scanning Android Tutorial Exercise 2 ❯

2.2 Verilog Combinational Logic UDP

Category Advanced Verilog Tutorial

NAND Gate Example

In combinational logic UDP, the state table specifies different input combinations and their corresponding output values. Any unspecified combination results in an output value of x.

A simple NAND gate UDP can be represented as follows:

primitive nand_my(out, a, b);
   output       out ;
   input        a, b ;

   table
    //a         b       :       out ;
      0         0       :       1 ;
      0         1       :       1 ;
      1         0       :       1 ;
      1         1       :       0 ;
   endtable
endprimitive

As explained in the previous section, the port list and declaration part can be modified to:

primitive nand_my(
  output       out,
  input        a, b);
  ......
endprimitive

State Table Entries

The syntax format for each row in the state table representing combinational logic is as follows:

<input1>  <input2>  ...  <inputN>  :  <output> ;

1. The order of input signals in the state table must match the order in the UDP port list.
1. Inputs and outputs are separated by a colon :.
1. Each row in the state table ends with a semicolon ;.
1. All combinations of input items that can produce a definite output value must be listed in the state table, otherwise, an x value will be output.

For example, in the above UDP nand_my, if a=0, b=x, the output out = x because this combination option cannot be found in the table. Therefore, when writing a UDP, all possible combinations of inputs must be considered comprehensively.

The state table of UDP nand_my can be modified to:

table
    //a         b       :       out ;
      0         0       :       1 ;
      0         1       :       1 ;
      1         0       :       1 ;
      1         1       :       0 ;

      0         x       :       1 ;
      x         0       :       1 ;
   endtable

Don't Care Terms

In UDP nand_my, when either a or b input is 0, the output is 1.

Input signals that do not affect the output result are called don't care terms and can be represented by a question mark "?". The "?" entries in the state table will automatically expand to 0, 1, or x.

Therefore, the state table of UDP nand_my can be modified to:

table
    //a         b       :       out ;
      0         ?       :       1 ;
      ?         0       :       1 ;
      1         1       :       0 ;

      //The following combinations will output x, so they can also be omitted, as Verilog defaults to output x
      1         x       :       x ;
      x         1       :       x ;
   endtable

UDP Instantiation

The UDP call format is identical to that of built-in gate-level primitives.

Using the above UDP nand_my to complete the simulation of the D flip-flop as described in 《1.3 Gate Delay》.

Removing the delay information, the D flip-flop model is as follows.

Example

module D_TRI(
            input       D, CP,
            output      Q, QR);

   //part1, not gate
   wire          CPN, DN ;
   not           (CPN, CP);
   not           (DN, D);

   //part2, master trigger
   wire          G3O, G4O ;
   nand_my       (G3O, D, CP);
   nand_my       (G4O, DN, CP);
   wire          G1O, G2O ;
   nand_my       (G1O, G3O, G2O);
   nand_my       (G2O, G4O, G1O);

   //part3, slave trigger
   wire          G7O, G8O ;
   nand_my       (G7O, G1O, CPN);
   nand_my       (G8O, G2O, CPN);
   wire          G5O, G6O ;
   nand_my       (G5O, G7O, G6O);
   nand_my       (G6O, G8O, G5O);

   assign        Q = G5O ;
   assign        QR = G6O ;

endmodule

The testbench remains unchanged, and the simulation results are as follows.

As shown in the figure, the flip-flop captures the signal at D port at the falling edge of the clock CP and transfers it to Q/QR, maintaining it within a single cycle.

The NAND gate function completed by UDP is correct.

Source Code Download

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-0.1 Digital Logic Design -0.2 Verilog Coding Style -0.3 Verilog Code Specification -1.1 Verilog Gate Types -1.2 Verilog Switch-Level Modeling -1.3 Verilog Gate Delay -2.1 Verilog UDP Basics

2.2 Verilog Combinational Logic UDP -2.3 Verilog Sequential Logic UDP -3.1 Verilog Delay Models -3.2 Verilog specify Block Statements -3.3 Verilog Setup and Hold Time -3.4 Verilog Timing Checks -3.5 Verilog Delay Backannotation -4.1 Verilog Synchronous and Asynchronous -4.2 Verilog Clock Domain Crossing: Slow to Fast -4.3 Verilog Clock Domain Crossing: Fast to Slow -4.4 Verilog FIFO Design -5.1 Verilog Reset Introduction -5.2 Verilog Clock Introduction -5.3 Verilog Clock Division -5.4 Verilog Clock Switching -6.1 Verilog Low Power Introduction -6.2 Verilog System-Level Low Power Design -6.3 Verilog RTL-Level Low Power Design (Part 1) -6.4 Verilog RTL-Level Low Power Design (Part 2) -7.1 Verilog Display Tasks -7.2 Verilog File Operations -7.3 Verilog Random Numbers and Probability Distribution -7.4 Verilog Real to Integer Conversion -7.5 Verilog Other System Tasks -8.1 Verilog PLI Introduction -8.2 Verilog TF Subroutines -8.3 Verilog TF Subroutine List -8.4 Verilog ACC Subroutines -8.5 Verilog ACC Subroutine List -9.1 Verilog Logic Synthesis -9.2 Verilog Synthesizable Design

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❮ Python Openssl Vulnerability Scanning Android Tutorial Exercise 2 ❯