1.2 Introduction to Verilog

❮ Android Tutorial Canvas Api1 Android Tutorial Autocompletetextview ❯

1.2 Introduction to Verilog

Category Verilog Tutorial

Verilog has strong capabilities for circuit description and modeling, allowing it to describe and model digital systems at multiple levels. Therefore, it has demonstrated robust vitality and potential in simplifying hardware design tasks, enhancing design efficiency and reliability, improving language readability, and facilitating hierarchical and structured design.

Development History

In 1983, Verilog was initially created by Phil Moorby of Gateway Design Automation (GDA) as an internal language for simulators, primarily used for logic modeling and simulation verification, and was widely adopted.
In 1989, GDA was acquired by Cadence, making Verilog the private property of Cadence.
In 1990, Cadence established the Open Verilog International (OVI) organization to publicly release Verilog and promote its development in the public domain.
In 1992, OVI decided to push for the adoption of the Verilog OVI standard as an IEEE (The Institute of Electrical and Electronics Engineers) standard.
In 1995, OVI's efforts succeeded, and IEEE established the first international standard for Verilog HDL, known as IEEE Std 1364-1995, or Verilog 1.0.
In 2001, IEEE released the second standard for Verilog (Verilog 2.0), known as IEEE Std 1364-2001, or the Verilog-2001 standard. Due to Cadence's influence in the field of integrated circuit design and Verilog's simplicity and ease of use, Verilog became the most popular hardware description language for circuit design.

Main Features

Below are the main features of Verilog:

Allows design modeling in three different ways: behavioral description—using procedural constructs for modeling; dataflow description—using continuous assignment statements for modeling; structural approach—using gate and module instantiation statements for description.
Two types of data types: wire data type and register (reg) data type, where wire represents connections between physical components and register represents abstract data storage components.
Capable of describing hierarchical designs, using module instantiation to describe any level.
User-defined primitives (UDP) are highly flexible. Primitives can be either combinational or sequential logic.
Provides language constructs to specify delay from port to port in a design, as well as path delay and timing checks.
Supports other programming language interfaces (PLI) for further extension. PLI allows external functions to access internal information of Verilog modules, providing richer testing methods for simulation.
The same language can be used to generate simulation stimuli and specify test constraints.
When designing logical functions, designers do not need to consider factors that do not affect logic functions, such as process, temperature, etc.
...

Main Applications

Application-Specific Integrated Circuits (ASIC), which are independent integrated circuit devices with specific and special functions.

Verilog, as a hardware description language, is primarily used to generate ASICs.

It is mainly accomplished through three avenues:

1. Programmable Logic Devices

FPGA and CPLD are the mainstream devices for this approach. They directly serve users, offering great flexibility and universality, quick implementation, easy testing, high development efficiency, and low cost.

2. Semi-custom or Full-custom ASIC

In simple terms, this involves using Verilog to design special-purpose chips with certain functions. Depending on the differences in basic cell technology, it can be divided into gate array ASIC, standard cell ASIC, and full-custom ASIC.

3. Mixed ASIC

Primarily refers to devices that have both user-oriented FPGA programmable logic functions and logic resources, as well as hardware standard cell modules that can be easily called and configured, such as CPUs, RAM, phase-locked loops, multipliers, etc.

-1.1 Verilog Tutorial