4.7 Verilog Loop Statements

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4.7 Verilog Loop Statements

Category Verilog Tutorial

Keywords: while, for, repeat, forever

There are four types of Verilog loop statements: while, for, repeat, and forever loops. Loop statements can only be used within always or initial blocks but can include delay expressions.

while Loop

The syntax for the while loop is as follows:

while (condition) begin
    …
end

The termination condition for the while loop is when the condition is false.

If the condition is false when the while loop starts executing, the loop statement will not execute at all.

Of course, when there is only one execution statement, the keywords begin and end can be omitted.

The following code, when executed, counter is executed 11 times.

Example

`timescale 1ns/1ns
 
module test ;
 
    reg [3:0]    counter ;
    initial begin
        counter = 'b0 ;
        while (counter<=10) begin
            #10 ;
            counter = counter + 1'b1 ;
        end
    end
 
   //stop the simulation
    always begin
        #10 ;  if ($time >= 1000) $finish ;
    end
 
endmodule

Simulation results are as follows:

for Loop

The syntax for the for loop is as follows:

for(initial_assignment; condition ; step_assignment)  begin
    …
end

initial_assignment is the initial condition.

condition is the termination condition, and the loop is exited immediately when the condition is false.

step_assignment is the process of assigning a value to change the control variable, usually increasing or decreasing the loop variable count.

Generally speaking, because the initial condition and increment operations are already included in the for loop, the for loop is more compact than the while loop, but it is not always possible to replace the while loop with a for loop.

The following example of the for loop achieves the same effect as the example in the while loop. It should be noted that i = i + 1 cannot be written in the form of i++ as in C language, and i = i -1 cannot be written in the form of i --.

Example

// for loop statement
integer      i ;
reg [3:0]    counter2 ;
initial begin
    counter2 = 'b0 ;
    for (i=0; i<=10; i=i+1) begin
        #10 ;
        counter2 = counter2 + 1'b1 ;
    end
end

repeat Loop

The syntax for the repeat loop is as follows:

repeat (loop_times) begin
    …
end

The function of repeat is to perform a fixed number of loops, and it cannot determine whether the loop continues to execute with a logical expression like the while loop. The number of times for the repeat loop must be a constant, variable, or signal. If the loop count is a variable signal, the loop count is the value of the variable signal when the repeat loop starts executing. Even if the value of the variable signal representing the loop count changes during execution, the number of times the repeat is executed will not change.

The following example of the repeat loop achieves the same effect as the example in the while loop.

Example

// repeat loop statement
reg [3:0]    counter3 ;
initial begin
    counter3 = 'b0 ;
    repeat (11) begin  //repeat 11 times
        #10 ;
        counter3 = counter3 + 1'b1 ;
    end
end

The following example of the repeat loop achieves the function of continuously storing 8 pieces of data:

Example

always @(posedge clk or negedge rstn) begin
    j = 0  ;
    if (!rstn) begin
        repeat (8) begin
            buffer[j]   <= 'b0 ;      //Non-delayed assignment, that is, set to 0 at the same time
            j = j + 1 ;
        end
    end
    else if (enable) begin
        repeat (8) begin
            @(posedge clk) buffer[j]    <= counter3 ;       //Assign at the next positive edge of clk
            j = j + 1 ;
        end
     end
end

Simulation results are shown in the following figure.

As shown in the

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