6.5 Avoiding Latches in Verilog
Category Verilog Tutorial
Keywords: Flip-flop, Latch
Meaning of Latch
A latch is a level-triggered storage element whose data storage action depends on the logic level of the input clock (or enable) signal. The output only changes in response to the data input when the latch is enabled.
When the level signal is inactive, the output signal changes with the input signal, just like it has passed through a buffer; when the level is active, the output signal is latched. Any change in the excitation signal will directly cause a change in the latch's output state, which may potentially lead to oscillation due to unstable transient characteristics.
The latch schematic is as follows:
A flip-flop is an edge-sensitive storage element, and the data storage action (state transition) is synchronized by the rising or falling edge of a certain signal (restricting the state transition of the storage element within a very short time).
The flip-flop schematic is as follows:
A register in Verilog is used to temporarily store data and results involved in calculations. When a variable is declared as a register, it can be synthesized into a flip-flop, a latch, or even a wire variable. However, in most cases, we want it to be synthesized into a flip-flop, but sometimes due to code writing issues, it may be synthesized into an undesired latch structure.
The main hazards of latches are:
1) The input state may change multiple times, which is prone to glitches, increasing the uncertainty of the next level of circuit;
2) In most FPGA resources, more resources may be needed to implement a latch structure than a flip-flop;
3) The emergence of latches makes static timing analysis more complex.
Latches are often used for gated clock (clock gating) control. Generally, in design, we should avoid the generation of latches.
Incomplete if Structure
In combinational logic, an incomplete if-else structure can produce a latch.
For example, in the following model, the if statement lacks an else structure, and the system defaults to the else branch where the value of the register q remains unchanged, that is, it has the function of storing data, so the register q will be synthesized into a latch structure.
Example
module module1_latch1(
input data,
input en,
output reg q);
always @(*) begin
if (en) q = data;
end
endmodule
There are mainly two ways to avoid such a latch, one is to complete the if-else structure, or to assign an initial value to the signal.
For example, the always statement in the above model can be changed to the following two forms:
Example
// Complete the conditional branch structure
always @(*) begin
if (en) q = data;
else q = 1'b0;
end
// Assign initial value
always @(*) begin
q = 1'b0;
if (en) q = data; // If en is valid, rewrite the value of q, otherwise q will remain 0
end
However, in sequential logic, an incomplete if-else structure will not produce a latch, such as the following model.
This is because the q register has a storage function, and its value will only change on the edge of the clock, which is the characteristic of a flip-flop.
Example
module module1_ff(
input clk,
input data,
input en,
output reg q);
always @(posedge clk) begin
if (en) q <= data;
end
endmodule
In combinational logic, when there are many assignment statements in the conditional statement, incompleteness in each branch condition will also produce a latch.
In fact, looking at the logic of each signal separately, this is also equivalent to an incomplete if-else structure, where the relevant register signals lack assignment behavior under other conditions. For example:
Example
module module1_latch11(
input data1,
input data2,
input en,
output reg q1,
output reg q2);
always @(*) begin
if (en) q1 = data1;
else q2 = data2;
end
endmodule
This situation can also be avoided by supplementing the complete assignment statements or assigning initial values. For example:
Example
``` always @(*) begin // q1 = 0; q2 = 0; // Or assign initial values to q1/q2 here if (en) begin
6.5 Avoiding Latches in Verilog