8.1 Verilog Numerical Conversion
Category Verilog Tutorial
This section primarily summarizes the decimal and binary representations of signed numbers in Verilog, along with some numerical transformations.
Define a binary data dbin in two's complement format with a width of DW, which represents a signed decimal number ddec.
reg [DW-1:0] dbin;
1. Decimal Signed to Binary Two's Complement
The two's complement of a positive number is the same as its original code.
If the decimal number ddec is negative, there are two main methods to calculate its corresponding two's complement:
Change the most significant bit (MSB) of ddec to 1, and invert the remaining numerical part then add one
For example, the numerical part of the 4-bit number -6 is 4'b0110, which becomes 4'b0010 after inversion and adding one, and then changing the MSB results in 4'b1010.
dbin = {1'b1, ~3'b110 + 3'b1}; // 4'b1010
Directly add the negative number ddec to its maximum numerical range (referred to as the modulus)
For example, the sum of the 4-bit number -6 and 16 (2 to the power of 4) is 10, which corresponds to 4'b1010.
dbin = ddec + (1<<4); // 4'b1010
2. Binary Two's Complement to Decimal Signed
When the MSB of dbin is 0, its numerical value is the represented positive decimal number.
When the MSB of dbin is 1, there are two main methods to calculate the represented signed decimal number:
Invert dbin, add one, and add the sign bit
For example, the two's complement of the 4-bit number -6 is 4'b1010, which becomes 4'b0110 after inversion and adding one, and adding the sign bit results in -6.
ddec = -(~4'b1010 + 1'b1); // -6
Subtract the unsigned numerical value of dbin from its maximum numerical range
For example, the two's complement of the 4-bit number -6 is 4'b1010, which has an unsigned value of 10, and 10 minus 16 results in -6.
ddec = dbin - (1<<4); // -6
3. Absolute Value
The logic to find the absolute value of dbin is as follows:
dbin_abs = (dbin[DW-1] ? ~dbin : dbin) + 1'b1;
For example, the two's complement of the 4-bit number -6 is 4'b1010, which becomes 4'b0110 (6) after inversion and adding one, which is the absolute value of -6.
However, if dbin is positive, adding one results in a value one greater than its true absolute value. This step is only to make the absolute values of positive numbers consistent with those of negative numbers, as the representation of signed numbers includes one more negative value due to the presence of zero.
4. Signed to Unsigned Conversion
The logic to extend a signed number into an unsigned number is as follows:
dbin_unsigned = {!dbin[DW-1], dbin[DW-2:0]};
For example:
4'b1010 (-6) -> 4'b0010 (2), 4'b0010 (2) -> 4'b1010 (10)
The conversion principle is to shift the numerical range of the data above zero. After converting a signed number to an unsigned number, the relative difference between the data remains unchanged.
5. Sign Bit Extension
Sometimes, it is necessary to extend the bit width of a signed number during calculations. Assuming the bit width increment is W, the extension logic is as follows:
dbin_extend = {{(W){dbin[DW-1]}}, dbin};
The extension principle is to fill the highest bit representing the sign bit into the extended high-order data bits.
For example, 4'b1010 (-6) extended to 8 bits becomes 8'b11111010, and its corresponding negative number is still -6.
-1.3 Verilog Environment Setup
-2.2 Verilog Numerical Representation
-2.5 Verilog Compile Instructions
-3.1 Verilog Continuous Assignment
-4.1 Verilog Process Structure
-4.2 Verilog Process Assignment
-4.5 Verilog Conditional Statements
-4.8 Verilog Procedural Continuous Assignment
-5.1 Verilog Modules and Ports
-5.2 Verilog Module Instantiation
-5.3 Verilog Parameterized Instantiation
-6.4 Verilog Competition and Hazards
-6.6 Verilog Simulation Stimulus
-7.2 Verilog Parallel FIR Filter Design
-7.3 Verilog Serial FIR Filter Design
-7.4 Verilog CIC Filter Design
- 8.1 Verilog Numerical Conversion
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