1.3 Verilog Gate Delays
Classification Verilog Tutorial Advanced Section
Keywords: Gate Delay, D Flip-Flop
Types of Gate Delays
The gate-level circuits introduced in the previous two sections are delay-free, but actual gate-level circuits do have delays.
In Verilog, users are allowed to use gate delays to define the transmission delay from the input to the output signal.
There are mainly three types of gate delays.
Rise Delay
The transition time required for the output of a gate to change from 0, x, z to 1 when the input of the gate changes is called the rise delay.
Fall Delay
The transition time required for the output of a gate to change from 1, x, z to 0 when the input of the gate changes is called the fall delay.
Turn-off Delay
The turn-off delay refers to the transition time required for the output of a gate to change from 0, 1, x to a high-impedance state z.
The transition time required for the gate output to change from 0, 1, z to x is not explicitly defined, but the time it takes can be determined by the other delay types, which is the smallest of the above three delays.
Gate delays can be defined when instantiating a gate unit, and the definition format is as follows:
gate_type [delay] [instance_name] (signal_list) ;
The number of delays can be 0, 1, 2, or 3.
The following table explains the value of each type of delay when different numbers of delays are specified.
| Delay Type | No Delay | 1 Delay (d) | 2 Delays (d1, d2) | 3 Delays (d1, d2, d3) |
|---|---|---|---|---|
| Rise | 0 | d | d1 | d1 |
| Fall | 0 | d | d2 | d2 |
| Turn-off | 0 | d | min(d1, d2) | d3 |
| to_x | 0 | d | min(d1, d2) | min(d1, d2, d3) |
If the user does not specify a delay value, the default delay is 0.
If the user specifies 1 delay value, all types of delay values are this value.
If the user specifies 2 delay values, they represent the rise delay and fall delay, respectively, and the turn-off and "to_x" delays are the smallest of these 2 delay values.
If the user specifies 3 delay values, they represent the rise delay, fall delay, and turn-off delay, respectively, and the "to_x" delay is the smallest of these 3 delay values.
The instantiation of a gate-level unit with delay values is as follows:
Example
//rise, fall, and turn-off delays are all 1
and #(1) (OUT1, IN1, IN2) ;
//rise delay = 2.1, fall delay = 2, turn-off delay = 2
or #(2.1, 2) (OUT2, IN1, IN2) ;
//rise delay = 2, fall delay = 1, turn-off delay = 1.3
bufif0 #(2, 1, 1.3) (OUT3, IN1, CTRL) ;
It should be noted that multi-input gates (such as AND gates) and multi-output gates (such as NOT gates) can only define up to 2 delays, as the output will not be z.
Tri-state gates and single-pole single-throw (SPST) switches (such as MOS and CMOS transistors) can define 3 delays.
Pull-up and pull-down gate circuits will not have any delays, as they represent a hardware attribute, the pull-up and pull-down states will not change, and there is no output value.
Bidirectional switches (tran) have no delay when transmitting signals and do not allow delay definitions to be added.
Bidirectional switches with a control terminal (tranif1, tranif0) will have an on or off delay when switching, and you can specify 0, 1, or 2 delays for such bidirectional switches, for example:
Example
//turn-on and turn-off delays are both 1
tranif0 #(1) (inout1, inout2, CTRL);
//turn-on delay = 1, turn-off delay = 1.2
tranif1 #(1, 1.2) (inout3, inout4, CTRL);
Minimum/Typical/Maximum
// $display("---gyc---%d", $time); if ($time >= 1000) begin $finish; end end endmodule // test
The simulation results are as follows.
As can be seen from the figure, both the Q/QR signals captured the D terminal signal on the falling edge of the clock CP and remained unchanged within a single cycle, and the output has a delay.
By zooming in on the moment of cap3 and tracking the delay, the following figure is shown.
There is a rising delay from the CP end to the CPN end, with a time of 110ps;
There is a falling delay from the CPN end to the G8O end, with a time of 70ps;
There is a rising delay from the G8O end to the G6O end, with a time of 110ps;
There is a falling delay from the G6O end to the Q end, with a time of 70ps;
A total of 360ps, which is consistent with the set gate delay.
Download the source code for this section
-1.2 Verilog Switch-Level Modeling
- 1.3 Verilog Gate Delay
-2.1 Basic Knowledge of Verilog UDP
-2.2 Verilog Combinational Logic UDP
-2.3 Verilog Sequential Logic UDP
-3.2 Verilog Specify Block Statements
-3.3 Verilog Setup and Hold Times
-3.5 Verilog Delay Back Annotation
-4.1 Verilog Synchronization and Asynchrony
-4.2 Verilog Cross-Clock Domain Transfer: Slow to Fast
-4.3 Verilog Cross-Clock Domain Transfer: Fast to Slow
-5.1 Introduction to Verilog Reset
-5.2 Introduction to Verilog Clock
-6.1 Introduction to Verilog Low Power
-6.2 System-Level Low Power Design in Verilog
-6.3 RTL-Level Low Power Design in Verilog (Part 1)
-6.4 RTL-Level Low Power Design in Verilog (Part 2)
-7.3 Verilog Random Numbers and Probability Distributions
-7.4 Verilog Real to Integer Conversion
-7.5 Other Verilog System Tasks
-8.1 Introduction to Verilog PLI
-8.3 List of Verilog TF Subprograms