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1.4 Verilog Design Method

Classification Verilog Tutorial

Design Method

The design of Verilog often adopts a top-down approach. This means that the top-level module functionality is defined first, followed by an analysis of the necessary sub-modules to constitute the top-level module; then each module is further decomposed and designed until it reaches the bottom-level functional blocks that cannot be further decomposed. In this way, a larger system can be refined into multiple smaller systems, which can be allocated in terms of time and workload to more personnel for design, thereby improving the design speed and shortening the development cycle.

Design Process

The design process of Verilog generally includes the following steps:

Requirements Analysis

Staff need to analyze and understand the functional requirements proposed by users, make an overall plan for the circuit system, form detailed technical indicators, and determine preliminary plans. For example, when designing a display screen, one needs to consider the power supply method, operating frequency, product size, cost, power consumption, and whether to use ASIC or select FPGA/CPLD devices for circuit implementation.

Functional Division

After correctly analyzing the user's circuit requirements, the overall design of the logical function can be carried out, designing the entire circuit's functionality, interface, and overall structure, considering the division and design ideas of functional modules, the interface and timing of each sub-module (including interface timing and internal signal timing), and reasonably allocating the design tasks of sub-modules to project team members.

Text Description

Any text editor can be used, or a dedicated HDL editing environment can be used to model the required digital circuit and save it as a .v file.

Functional Simulation (Pre-simulation)

Compile the modeling file and simulate the model circuit functionally to find and correct design errors.

At this time, the simulation verification does not consider timing factors such as signal delays, only verifying the correctness of the logic.

Logic Synthesis

Synthesis is the process of converting the high-level description of the design (Verilog modeling) into a gate-level netlist based on the standard cell library and specific design constraints. The purpose of logic synthesis is to produce a gate-level structure of the physical circuit and to optimize it to some extent in terms of logic and timing, seeking a balance between logic, area, and power consumption, and enhancing the testability of the circuit.

However, not all Verilog statements can be synthesized into logic units, such as timing statements.

Placement and Routing

Based on the netlist and constraint files output by logic synthesis, use the various basic standard cell libraries provided by the manufacturer to place and route the gate-level circuit. At this point, the digital circuit designed by Verilog has been designed into a digital circuit composed of standard cell libraries.

Timing Simulation (Post-simulation)

After placement and routing, the circuit model already contains timing information. Use the precise parameters obtained in the placement and routing to verify the timing of the circuit with simulation software. The differences in unit devices and placement and routing schemes can affect the timing of the circuit, and serious errors may occur. If errors occur, it may be necessary to modify the RTL (Register Transfer Level description, i.e., the original Verilog description) and repeat the subsequent steps. This process may be repeated multiple times until all errors are completely eliminated.

FPGA/CPLD Download or ASIC Manufacturing Process Production

After completing all the above steps, the target file of the designed digital circuit can be downloaded to the FPGA/CPLD chip through the development tool, and then debugged and verified on the circuit board.

If implementation on an ASIC is required, chip manufacturing is necessary. Generally, when manufacturing chips, it is also necessary to verify the logical function on the FPGA board card first.

-1.1 Verilog Tutorial

-1.2 Introduction to Verilog

-1.3 Building Verilog Environment

-2.1 Basic Syntax of Verilog

-2.2 Numerical Representation in Verilog

-2.3 Data Types in Verilog

-2.4 Expressions in Verilog

-2.5 Verilog Compilation Instructions

-3.1 Continuous Assignment in Verilog

-3.2 Timing Delay in Verilog

-4.1 Process Structures in Verilog

-4.2 Process Assignment in Verilog

-[4.3 Timing Control

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