4.2 Verilog Cross-Clock Domain Transfer: Slow to Fast
Category Advanced Verilog Tutorial
In theory, signals in the fast clock domain will always capture signals transmitted from the slow clock domain. Asynchronous transfer may lead to sampling errors, so synchronization is required. This type of synchronization is relatively simple and generally uses a double flip-flop buffering method, commonly known as the delay-clapping method.
Delay Clapping Method
The most commonly used synchronization method is the double flip-flop buffering method, commonly known as the delay-clapping method. Before an asynchronous signal enters another clock domain, the signal is buffered twice with two levels of flip-flops in a row, which can effectively reduce the metastability issues caused by unsatisfied timing. The circuit diagram is as follows.
In general design, using two levels of flip-flops for buffering can meet the design timing requirements. Extensive experiments have shown that triple flip-flop buffering can solve more than 99% of such asynchronous timing issues.
The Verilog description for two-level flip-flop delay-clapping and signal rising edge detection is as follows:
Example
module delay_clap(
input clk1, // Asynchronous slow clock
input sig1, // Asynchronous signal
input rstn, // Reset signal
input clk2, // Target fast clock domain clock
output sig2); // Synchronized signal in the fast clock domain
reg [2:0] sig2_r; // 3-level buffering, the first two levels for synchronization, the last two levels for edge detection
always @(posedge clk2 or negedge rstn) begin
if (!rstn) sig2_r <= 3'b0;
else sig2_r <= {sig2_r[1:0], sig1}; // Buffering
end
assign sig2 = sig2_r[1] && !sig2_r[2]; // Rising edge detection
Delay Sampling Method
This method is mainly for multi-bit wide data transfer.
For example, when the frequency ratio of two asynchronous clocks is 5, the data enable signal can be buffered with a 2-level clapping method first, and then the data signal from the slow clock domain can be captured in the fast clock domain.
The basic idea of this method is to ensure the moment when the signal is safely captured, without the need to synchronize multi-bit wide data signals, which can save some hardware resources.
The Verilog description for delay sampling using the clapping method is as follows.
Example
// Synchronization module with a working clock of 100MHz
// Asynchronous data comes from a module with a working clock of 20MHz
module delay_sample(
input rstn,
input clk1,
input [31:0] din,
input din_en,
input clk2,
output [31:0] dout,
output dout_en);
// Sync din_en
reg [2:0] din_en_r;
always @(posedge clk2 or negedge rstn) begin
if (!rstn) din_en_r <= 3'b0;
else din_en_r <= {din_en_r[1:0], din_en};
end
wire din_en_pos = din_en_r[1] && !din_en_r[2];
// Sync data
reg [31:0] dout_r;
reg dout_en_r;
always @(posedge clk2 or negedge rstn) begin
if (!rstn) dout_r <= 'b0;
else if (din_en_pos) dout_r <= din;
end
// dout_en delay
always @(posedge clk2 or negedge rstn) begin
if (!rstn) dout_en_r <= 1'b0;
else dout_en_r <= din_en_pos;
end
assign dout = dout_r;
assign dout_en = dout_en_r;
endmodule
The timing result diagram for this method is shown below.
It is clear that at time t2 in the clk2 clock domain, sampling and buffering the data is much safer than at time t1.
However, if there is no data enable signal din_en in the slow clock domain, or the data enable signal is always valid, the method of detecting the rising edge of the data enable signal in the fast clock domain will fail. Because the data enable signal is always valid, except for the first data, the fast clock domain will not be able to detect the transmission time of subsequent data.
The solution is to detect the edge of the slow clock signal in the fast clock domain.
If the