3.1 Verilog Delay Models

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3.1 Verilog Delay Models

Classification Advanced Verilog Tutorial

Keywords: Distributed Delay, Lumped Delay, Path Delay

Most previous simulations were to verify the correctness of digital circuit functionality, with ideal signal transmission and no delays. However, actual logic components and their transmission paths will have delays. Therefore, it is necessary to check whether the delays in the design meet the timing constraints of the actual circuit. Timing simulation can be used to check the timing, which means adding delay information consistent with the actual situation to components or paths during simulation and performing related calculations to determine if the timing is met.

Static Timing Analysis (STA) is also a timing verification technique. It does not care about the correctness of the logic function, but only calculates and analyzes the timing in the design to determine whether there is a design that violates the timing constraints. STA analysis is fast and can quickly locate problems, but it will ignore some asynchronous issues.

So "STA + Timing Simulation" is a relatively comprehensive and safe timing verification method. This tutorial only provides a brief introduction to timing simulation and does not discuss STA for the time being.

There are mainly 3 delay models: Distributed Delay, Lumped Delay, and Path Delay.

Distributed Delay

Distributed Delay requires defining delays for each independent component in the circuit, with different paths having different delays, as shown in the figure below.

The Verilog model for distributed delay is basically consistent with the way of instantiating logical gate units and specifying delay values.

Example

module and4(
    output   out,
    input    a, b, c, d);

    wire     an1, an2;
    and #1    (an1, a, b);
    and #2    (an2, c, d);
    and #1.5  (out, an1, an2);
endmodule

Distributed delay can also be explained using the continuous assignment statement assign.

Example

module and4(
    output   out,
    input    a, b, c, d);

    wire     an1, an2;
    assign #1 an1 = a & b;
    assign #2 an2 = c & d;
    assign #1.5 out = an1 & an2;
endmodule

Lumped Delay

Lumped Delay is to concentrate the total delay of all paths on the last gate unit.

The delay on the last gate unit will vary depending on the path, and the maximum delay is taken as the delay of the last gate unit.

The above distributed delay diagram is transformed into a lumped delay diagram, as shown below.

The Verilog model for lumped delay is as follows.

Example

module and4(
    output   out,
    input    a, b, c, d);

    wire     an1, an2;
    and       (an1, a, b);
    and       (an2, c, d);
    and #3.5  (out, an1, an2); //set the max delay at the last gate
endmodule

Path Delay

Path Delay is to specify the delay time for all paths from each input pin to each output pin.

The schematic diagram of path delay is as follows.

The path delay model requires the keyword specify to define.

The Verilog model for path delay is as follows, and the specific definition method will be introduced in detail in the next section.

Example

module and4(
    output   out,
    input    a, b, c, d);

    specify
        (a => out) = 2.5;
        (b => out) = 2.5;
        (c => out) = 3.5;
        (d => out) = 3.5;
    endspecify

    wire     an1, an2;
    and       (an1, a, b);
    and       (an2, c, d);
    and       (out, an1, an2);
endmodule

Comparison of Delay Models

Distributed Delay: Distributed Delay disperses the delay time on each gate unit, but still cannot describe the difference in delay on different pins within the basic unit. When the design scale increases, the structure will become more complex.
Lumped Delay: This model is simple and suitable for small-scale circuits, but it cannot describe the delay of different paths from the input end to the output end.
Path Delay: It specifies the delay from pin to pin, and the delay information is relatively complete. Although there is more information, it is also easier to implement for large-scale circuits. Because the designer does not need to care about the internal implementation logic of the module, just need to understand the delay from

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